Add initial clock driver for Allwinner H3/H5.
- Implement USB bus and USB clocks via ccu_clk_map descriptor
for H3/H5, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor
for H3/H5, so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/clk/sunxi/Kconfig | 7 +++
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h3.c | 97 ++++++++++++++++++++++++++++++++++++++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_h3.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 041d711e58..c3713bbac2 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -9,6 +9,13 @@ config CLK_SUNXI
if CLK_SUNXI
+config CLK_SUN8I_H3
+ bool "Clock driver for Allwinner H3/H5"
+ default MACH_SUNXI_H3_H5
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner H3/H5 SoC.
+
config CLK_SUN50I_A64
bool "Clock driver for Allwinner A64"
default MACH_SUN50I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index fb20d28333..dec49f27a1 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
+obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
new file mode 100644
index 0000000000..0b7f4947dd
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <ja...@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+static struct ccu_clk_map h3_clks[] = {
+ [CLK_BUS_OTG] = { 0x060, BIT(23), NULL },
+ [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL },
+ [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL },
+ [CLK_BUS_EHCI2] = { 0x060, BIT(26), NULL },
+ [CLK_BUS_EHCI3] = { 0x060, BIT(27), NULL },
+ [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL },
+ [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },
+ [CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL },
+ [CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },
+
+ [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL },
+ [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL },
+ [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL },
+ [CLK_USB_PHY3] = { 0x0cc, BIT(11), NULL },
+ [CLK_USB_OHCI0] = { 0x0cc, BIT(16), NULL },
+ [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL },
+ [CLK_USB_OHCI2] = { 0x0cc, BIT(18), NULL },
+ [CLK_USB_OHCI3] = { 0x0cc, BIT(19), NULL },
+};
+
+static struct ccu_reset_map h3_resets[] = {
+ [RST_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_USB_PHY1] = { 0x0cc, BIT(1) },
+ [RST_USB_PHY2] = { 0x0cc, BIT(2) },
+ [RST_USB_PHY3] = { 0x0cc, BIT(3) },
+
+ [RST_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
+ [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
+ [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
+ [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
+ [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
+ [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
+ [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
+ [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
+};
+
+static const struct ccu_desc sun8i_h3_ccu_desc = {
+ .clks = h3_clks,
+ .num_clks = ARRAY_SIZE(h3_clks),
+
+ .resets = h3_resets,
+ .num_resets = ARRAY_SIZE(h3_resets),
+};
+
+static int h3_clk_probe(struct udevice *dev)
+{
+ struct sunxi_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+ if (!priv->desc)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int h3_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, 53);
+}
+
+static const struct udevice_id h3_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-h3-ccu",
+ .data = (ulong)&sun8i_h3_ccu_desc },
+ { .compatible = "allwinner,sun50i-h5-ccu",
+ .data = (ulong)&sun8i_h3_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun8i_h3) = {
+ .name = "sun8i_h3_ccu",
+ .id = UCLASS_CLK,
+ .of_match = h3_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = h3_clk_probe,
+ .bind = h3_clk_bind,
+};
--
2.18.0.321.gffc6fa0e3
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