On 07/19/2018 07:57 AM, Michal Simek wrote: > On 18.7.2018 22:11, Marek Vasut wrote: >> On 07/18/2018 04:57 PM, Michal Simek wrote: >>> On 18.7.2018 16:24, Marek Vasut wrote: >>>> On 07/18/2018 04:18 PM, Michal Simek wrote: >>>>> On 18.7.2018 16:15, Marek Vasut wrote: >>>>>> On 07/18/2018 04:00 PM, Michal Simek wrote: >>>>>>> On 18.7.2018 14:54, Marek Vasut wrote: >>>>>>>> On 07/18/2018 02:51 PM, Michal Simek wrote: >>>>>>>>> There shouldn't be a need to call private spl_load_fpga_image() >>>>>>>>> because the whole sequence should be already handled by fpga_load(). >>>>>>>>> The patch let spl_load_fit_image() to load data to right location >>>>>>>>> based >>>>>>>>> on "load" property in FIT and then call fpga_load(). >>>>>>>> >>>>>>>> NAK >>>>>>>> >>>>>>>> This breaks Arria10, sorry. The private loading function is needed on >>>>>>>> Arria10 as the whole bitstream is not available in RAM and needs to be >>>>>>>> loaded piece by piece, see [1] >>>>>>>> >>>>>>>> [1] >>>>>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=blobdiff;f=arch/arm/mach-socfpga/spl.c;h=82adb5dfb8de62e3d928f6f4405705f3f32a780c;hp=7ee988a2d59831ec6bff927b2a5fdad7f57da055;hb=21f835ebf2b40fc8a3e8b818c5c5ba2555dd7c65;hpb=bd198801cb95b5a8460c95a762cc4a9a44ca85ef >>>> >>>> [...] >>>>>>> The second solution is to check if load address is not 0 and call >>>>>>> fpga_load only for that. In this case there is a need to check size for >>>>>>> SPL. >>>>>> >>>>>> 0 is a valid load address, so no. >>>>> >>>>> Then new Kconfig option is another way to go now. >>>> >>>> No, the firmware loader is a way to go. Sadly, it's still work in progress. >>> >>> I have looked at that series and it will take some time to get it done >>> but even that series has no user and also only support filesystems. >>> Which is fine but not enough and support for RAW mode is necessary too. >> >> It already took like a year and half I think ... well, better invest >> your resources in perfecting it for your usecase, for that's the way to go. > > I don't think so because for SPL boot we need support for a RAW mode. > >> >>> Anyway Luis sent series where this SPL fpga supported is requested to >>> add and I had this functionality in more raw state in Xilinx tree for >>> quite a long time and it is time to support it because on Zybo (because >>> of i2c eeprom) and also cc108 (because of uart routing via PL) fpga load >>> needs to be done in SPL and we need that support. >> >> Ha >> >>> I have not a problem to keep your code in SPL but I need a way to enable >>> fpga load directly with all that features like hashes which are already >>> available. GZIP can be added pretty easily too. >>> That's why please suggest a way what you are comfortable with not to >>> block functionality on these devices. >> >> Look at the A10 nand branch, it uses full fit with all the bells and >> whistles. Maybe that's the way to go if you have DRAM available. > > Enabling full fit should be possible but there is really no need to > enable more and more features for load something to fpga. SPL still > needs to fit to small space.
Bitrot protection is always a good idea when loading from raw storage. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
