On Wed, Jul 4, 2018 at 5:31 PM, Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> wrote: > This patch adds qspi driver support for ZynqMP SoC. This > driver is responsible for communicating with qspi flash > devices. > > Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> > --- > Changes for v7: > - Removed reading of mode, clock phase and polarity from ofdata_to_platdata > as drivercan get from spi-uclass if required
Thanks for your efforts. > > Changes for v6: > - Removed spi_flash.h inclusion and other unused macros > - Fixed coding style comments > - Removed tx_rx_mode in plat and removed preprobe routine. > - Used proper error codes > > Changed for v5: > - Removed zynqm_gqspi.h file which was added > by mistake. > > Changes for v4: > - Moved macro definitions back to .c > - Removed last_cmd and flash command checks in driver > - Used macros and GENMASK as per comments > - Removed debugs wherever commented. > - Modified set_mode routine as per comment > > Changes for v3: > - Renamed all macros, functions, files and configs as per comment > - Used wait_for_bit wherever required > - Removed unnecessary header inclusion > > Changes for v2: > - Rebased on top of latest master > - Moved macro definitions to .h file as per comment > - Fixed magic values with macros as per comment > --- > drivers/spi/Kconfig | 7 + > drivers/spi/Makefile | 1 + > drivers/spi/zynqmp_gqspi.c | 734 > +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 742 insertions(+) > create mode 100644 drivers/spi/zynqmp_gqspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 3532c2a..c3c424e 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -223,6 +223,13 @@ config ZYNQ_QSPI > Zynq QSPI IP core. This IP is used to connect the flash in > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > +config ZYNQMP_GQSPI > + bool "Configure ZynqMP Generic QSPI" > + depends on ARCH_ZYNQMP > + help > + This option is used to enable ZynqMP QSPI controller driver which > + is used to communicate with qspi flash devices. > + > endif # if DM_SPI > > config SOFT_SPI > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 5a2c00e..2187633 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o > obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o > obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o > obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o > +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o > diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c > new file mode 100644 > index 0000000..665f98e > --- /dev/null > +++ b/drivers/spi/zynqmp_gqspi.c > @@ -0,0 +1,734 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2018 Xilinx > + * > + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) > + */ > + > +#include <common.h> > +#include <asm/arch/clk.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/io.h> > +#include <clk.h> > +#include <dm.h> > +#include <malloc.h> > +#include <memalign.h> > +#include <spi.h> > +#include <ubi_uboot.h> > +#include <wait_bit.h> > + > +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) > +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) > +#define GQSPI_CONFIG_DMA_MODE (2 << 30) > +#define GQSPI_CONFIG_CPHA_MASK BIT(2) > +#define GQSPI_CONFIG_CPOL_MASK BIT(1) > + > +/* QSPI MIO's count for different connection topologies */ > +#define GQSPI_MIO_NUM_QSPI0 6 > +#define GQSPI_MIO_NUM_QSPI1 5 > +#define GQSPI_MIO_NUM_QSPI1_CS 1 These were not related to spi driver, let me know if you OK to remove while applying? All fine to me except the above, so Reviewed-by: Jagan Teki <ja...@openedev.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
