Hi Boris, Boris Brezillon <boris.brezil...@bootlin.com> wrote on Thu, 12 Jul 2018 00:44:44 +0200:
> On Wed, 11 Jul 2018 17:25:29 +0200 > Miquel Raynal <miquel.ray...@bootlin.com> wrote: > > > From: Boris Brezillon <boris.brezil...@bootlin.com> > > > > Add bindings for SPI NAND chips. > > > > Signed-off-by: Boris Brezillon <boris.brezil...@bootlin.com> > > Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com> > > --- > > doc/device-tree-bindings/mtd/spi-nand.txt | 27 +++++++++++++++++++++++++++ > > 1 file changed, 27 insertions(+) > > create mode 100644 doc/device-tree-bindings/mtd/spi-nand.txt > > > > diff --git a/doc/device-tree-bindings/mtd/spi-nand.txt > > b/doc/device-tree-bindings/mtd/spi-nand.txt > > new file mode 100644 > > index 0000000000..d55f80196c > > --- /dev/null > > +++ b/doc/device-tree-bindings/mtd/spi-nand.txt > > @@ -0,0 +1,27 @@ > > +SPI NAND flash > > + > > +Required properties: > > +- compatible: should be "spi-nand" > > +- reg: should encode the chip-select line used to access the NAND chip > > + > > +Optional properties > > +- spi-max-frequency: maximum frequency of the SPI bus the chip can operate > > at. > > + This should encode board limitations (i.e. max freq can't > > + be achieved due to crosstalk on IO lines). > > + When unspecified, the driver assumes the chip can run at > > + the max frequency defined in the spec (information > > + extracted chip detection time). > > +- spi-tx-bus-width: The bus width (number of data wires) that is used for > > MOSI. > > + Only encodes the board constraints (i.e. when not all IO > > + signals are routed on the board). Device constraints are > > + extracted when detecting the chip, and controller > > + constraints are exposed by the SPI mem controller. If this > > + property is missing that means no constraint at the board > > + level. > > +- spi-rx-bus-width: The bus width (number of data wires) that is used for > > MISO. > > + Only encodes the board constraints (i.e. when not all IO > > + signals are routed on the board). Device constraints are > > + extracted when detecting the chip, and controller > > + constraints are exposed by the SPI mem controller. If this > > + property is missing that means no constraint at the board > > + level. > > This section has been dropped from the Linux doc. Removed. Thanks, Miquèl _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
