On 07/11/2018 03:49 PM, Jason Rush wrote:
> On 7/11/2018 3:55 AM, Marek Vasut wrote:
>> On 07/11/2018 05:11 AM, Jason Rush wrote:
>> [...]
>>
>>>>>>> However, if I press the HPS_RST push button on the SoCKit (which is 
>>>>>>> connected
>>>>>>> to power on reset), occasionally U-Boot will lock up while booting.  It 
>>>>>>> always
>>>>>>> boots and operates correctly from the initial power on, but it almost 
>>>>>>> always
>>>>>>> fails to boot after pressing the HPS_RST button.
>>>>>>>
>>>>>>> Usually after pressing the HPS_RST button, U-Boot makes it past the 
>>>>>>> SPL, and
>>>>>>> hangs somewhere after the call to setup_reloc() in ./common/board_f.c.  
>>>>>>> Once
>>>>>>> it hangs there, pressing the HPS_RST button again usually causes the 
>>>>>>> SPL to
>>>>>>> hang while setting up the MMU (before my call to memset).  Eventually 
>>>>>>> the
>>>>>>> WDT kicks in, and it just keeps hanging up in the same place.  Once it 
>>>>>>> gets in
>>>>>>> this mode, the only way to recover it is by toggling power on the board.
>>>>>>>
>>>>>>> I spent a bunch of time today trying to track down where it was 
>>>>>>> hanging, but
>>>>>>> I couldn't pin point anything.  The MMU tables looked correct.  The MMU
>>>>>>> registers looked good.  I'm not sure the best way to debug what's going 
>>>>>>> on.
>>>>>> Try triggering warm reset and cold reset via the reset register:
>>>>>>
>>>>>> mw 0xffd05004 1
>>>>>> mw 0xffd05004 2
>>>>>>
>>>>>> Does it hang in one case and not in the other ?
>>>>>>
>>>>> It hangs in both cases.
>>>>>
>>>>> I did find that if I do not metset the last 1MiB of DRAM with the cache 
>>>>> on,
>>>>> both warm and cold resets work.
>>>>>
>>>>> I changed the ecc scrubbing to zero out the first 0x8000 bytes and the 
>>>>> last
>>>>> 0x10000 bytes before the MMU is setup and I enable dcache.  Then with
>>>>> the dcache enabled, I zero out the rest of memory.  The resets work in 
>>>>> this
>>>>> case as well.  So there seems to be some side effect of clearing out the
>>>>> relocate address space with the cache on.
>>>> Can you investigate ?
>>>>
>>> I'd be happy to investigate more, but I'm not really sure what
>>> my next step should be.
>>>
>>> Something appears to be happening differently when U-Boot
>>> relocates if the dcache is on.  But don't know how to track it
>>> down.
>> IIRC I disabled cache after scrubbing.
> 
> My mistake.  I did disable the dcache after scrubbing too.  The
> code is almost identical to the Arria10 code where after
> scrubbing it flushes the dcache, then turns it off.
> 
> The weird reset problems happens if I scrub the area where
> u-boot relocates to with the dcache on, then turn dcache off.
> 
> I tried to also tried turning the MMU off, but that didn't help.

Maybe there are some data used by the SPL there ? I think the SPL has
malloc area in RAM at some point.

-- 
Best regards,
Marek Vasut
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