On 06/28/2018 04:10 PM, Jagan Teki wrote: > Masking clock gate, reset register bits based on the > probed controller is proper only due to the assumption > that masking should start with 0 even thought the controller > has separate PHY or shared between OTG. > > unfortunately these are fixed due to lack of separate > clock, reset drivers. > > Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) > so we need to start reg_mask 0 - 2. > > This patch calculated the mask, based on the register base > so that we can get the proper bits to set with respect to > probed controller. > > We even do this masking by using PHY index specifier from dt, > but dev_read_addr_size is failing for 64-bit boards. > > Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Applied both -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
