On 05/28/2018 09:48 PM, Ramon Fried wrote:
On Mon, May 28, 2018 at 10:24 PM, Ramon Fried <[email protected]> wrote:
On Mon, May 28, 2018 at 10:19 PM, Jorge Ramirez-Ortiz
<[email protected]> wrote:
On 05/28/2018 09:12 PM, Tom Rini wrote:
On Wed, May 16, 2018 at 12:13:39PM +0300, Ramon Fried wrote:
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: Ramon Fried <[email protected]>
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed?
Sorry Tom, when I tested this on Friday it broke my 820 (I should have
reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I
was under the assumption that it won't get merged as it was
missing Reviewed-by.
Let me get back to you on these one in couple of hours.
Thanks,
Ramon.
I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the
clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master
to see if it's working ?
so just pull your master branch again and retest?
Thanks.
Ramon.
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