On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu
<siva.durga.palad...@xilinx.com> wrote:
> This patch adds qspi driver support for ZynqMP SoC. This
> driver is responsible for communicating with qspi flash
> devices.
>
> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com>
> ---
> Changes for v3:
> - Renamed all macros, functions, files and configs as per comment
> - Used wait_for_bit wherever required
> - Removed unnecessary header inclusion
>
> Changes for v2:
> - Rebased on top of latest master
> - Moved macro definitions to .h file as per comment
> - Fixed magic values with macros as per comment
> ---
> arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 ++++++
> drivers/spi/Kconfig | 7 +
> drivers/spi/Makefile | 1 +
> drivers/spi/zynqmp_gqspi.c | 670
> ++++++++++++++++++++++++
> 4 files changed, 832 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> create mode 100644 drivers/spi/zynqmp_gqspi.c
>
> diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
already asked you to move this header code in driver .c file
> new file mode 100644
> index 0000000..4b26d80
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> @@ -0,0 +1,154 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
[snip]
> + *
> + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <memalign.h>
> +#include <ubi_uboot.h>
> +#include <spi.h>
> +#include <spi_flash.h>
> +#include <asm/io.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/clk.h>
> +#include <clk.h>
> +#include <asm/arch/zynqmp_gqspi.h>
> +#include <wait_bit.h>
headers are inorder.
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct zynqmp_qspi_platdata {
> + struct zynqmp_qspi_regs *regs;
> + struct zynqmp_qspi_dma_regs *dma_regs;
> + u32 frequency;
> + u32 speed_hz;
> + unsigned int tx_rx_mode;
> +};
> +
> +struct zynqmp_qspi_priv {
> + struct zynqmp_qspi_regs *regs;
> + struct zynqmp_qspi_dma_regs *dma_regs;
> + u8 mode;
> + const void *tx_buf;
> + void *rx_buf;
> + unsigned int len;
> + int bytes_to_transfer;
> + int bytes_to_receive;
> + unsigned int is_inst;
> + unsigned int cs_change:1;
> +};
> +
> +static u8 last_cmd;
> +
> +static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
> +{
> + struct zynqmp_qspi_platdata *plat = bus->platdata;
> + u32 mode = 0;
> + u32 value;
> + int ret;
> + struct clk clk;
> + unsigned long clock;
> +
> + debug("%s\n", __func__);
> +
> + plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
> + GQSPI_REG_OFFSET);
> + plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
> + (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
> +
> + ret = clk_get_by_index(bus, 0, &clk);
> + if (ret < 0) {
> + dev_err(dev, "failed to get clock\n");
> + return ret;
> + }
> +
> + clock = clk_get_rate(&clk);
> + if (IS_ERR_VALUE(clock)) {
> + dev_err(dev, "failed to get rate\n");
> + return clock;
> + }
> + debug("%s: CLK %ld\n", __func__, clock);
> +
> + ret = clk_enable(&clk);
> + if (ret && ret != -ENOSYS) {
> + dev_err(dev, "failed to enable clock\n");
> + return ret;
> + }
> +
> + value = dev_read_u32_default(bus, "spi-rx-bus-width", 1);
> + switch (value) {
> + case 1:
> + break;
> + case 2:
> + mode |= SPI_RX_DUAL;
> + break;
> + case 4:
> + mode |= SPI_RX_QUAD;
> + break;
> + default:
> + printf("Invalid spi-rx-bus-width %d\n", value);
> + break;
> + }
> +
> + value = dev_read_u32_default(bus, "spi-tx-bus-width", 1);
> + switch (value) {
> + case 1:
> + break;
> + case 2:
> + mode |= SPI_TX_DUAL;
> + break;
> + case 4:
> + mode |= SPI_TX_QUAD;
> + break;
> + default:
> + printf("Invalid spi-tx-bus-width %d\n", value);
> + break;
> + }
> +
> + plat->tx_rx_mode = mode;
> +
> + plat->frequency = clock;
> + plat->speed_hz = plat->frequency;
> +
> + return 0;
> +}
> +
> +static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
> +{
> + u32 config_reg;
> + struct zynqmp_qspi_regs *regs = priv->regs;
> +
> + writel(GQSPI_GFIFO_SELECT, ®s->gqspisel);
> + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
> + writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
> + writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
> + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
> +
> + config_reg = readl(®s->confr);
> + config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
> + GQSPI_CONFIG_MODE_EN_MASK);
> + config_reg |= GQSPI_CONFIG_DMA_MODE |
> + GQSPI_GFIFO_WP_HOLD |
> + GQSPI_DFLT_BAUD_RATE_DIV;
> + writel(config_reg, ®s->confr);
> +
> + writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
> +}
> +
> +static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
> +{
> + u32 gqspi_fifo_reg = 0;
> +
> + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
> + GQSPI_GFIFO_CS_LOWER;
> +
> + return gqspi_fifo_reg;
> +}
> +
> +static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
> + u32 gqspi_fifo_reg)
> +{
> + struct zynqmp_qspi_regs *regs = priv->regs;
> + int ret = 0;
> +
> + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
> + GQSPI_TIMEOUT, 1);
> + if (ret)
> + printf("%s Timeout\n", __func__);
> +
> + writel(gqspi_fifo_reg, ®s->genfifo);
> +}
> +
> +static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
> +{
> + u32 gqspi_fifo_reg = 0;
> +
> + if (is_on) {
> + gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
> + gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
> + GQSPI_IMD_DATA_CS_ASSERT;
> + } else {
> + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
> + gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
> + }
> +
> + debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
> +
> + zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
> +}
> +
> +void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
> +{
> + struct zynqmp_qspi_platdata *plat = bus->platdata;
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> + struct zynqmp_qspi_regs *regs = priv->regs;
> + u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
> + u32 reqhz = 0;
> +
> + clk_rate = plat->frequency;
> + reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
> +
> + debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
> + __func__, reqhz, clk_rate, baudrateval);
> +
> + if (reqhz < GQSPI_FREQ_40MHZ) {
> + zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
> + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
> + TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
> + } else if (reqhz < GQSPI_FREQ_100MHZ) {
> + zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
> + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
> + TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
> + lpbkdlyadj = readl(®s->lpbkdly);
> + lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
> + datadlyadj = readl(®s->gqspidlyadj);
> + datadlyadj |= ((GQSPI_USE_DATA_DLY <<
> GQSPI_USE_DATA_DLY_SHIFT)
> + | (GQSPI_DATA_DLY_ADJ_VALUE <<
> + GQSPI_DATA_DLY_ADJ_SHIFT));
> + } else if (reqhz < GQSPI_FREQ_150MHZ) {
> + lpbkdlyadj = readl(®s->lpbkdly);
> + lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK) |
> + GQSPI_LPBK_DLY_ADJ_DLY_0);
> + }
> +
> + zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
> + tapdlybypass);
> + writel(lpbkdlyadj, ®s->lpbkdly);
> + writel(datadlyadj, ®s->gqspidlyadj);
> +}
> +
> +static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct zynqmp_qspi_platdata *plat = bus->platdata;
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> + struct zynqmp_qspi_regs *regs = priv->regs;
> + u32 confr;
> + u8 baud_rate_val = 0;
> +
> + debug("%s\n", __func__);
> + if (speed > plat->frequency)
> + speed = plat->frequency;
> +
> + /* Set the clock frequency */
> + confr = readl(®s->confr);
> + if (speed == 0) {
> + /* Set baudrate x8, if the freq is 0 */
> + baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
> + } else if (plat->speed_hz != speed) {
> + while ((baud_rate_val < 8) &&
> + ((plat->frequency /
> + (2 << baud_rate_val)) > speed))
> + baud_rate_val++;
> +
> + if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
> + baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
> +
> + plat->speed_hz = plat->frequency / (2 << baud_rate_val);
> + }
> + confr &= ~GQSPI_BAUD_DIV_MASK;
> + confr |= (baud_rate_val << 3);
> + writel(confr, ®s->confr);
> +
> + zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
> + debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_child_pre_probe(struct udevice *bus)
> +{
> + struct spi_slave *slave = dev_get_parent_priv(bus);
> + struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus->parent);
> +
> + slave->mode = plat->tx_rx_mode;
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_probe(struct udevice *bus)
> +{
> + struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> +
> + debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
> +
> + priv->regs = plat->regs;
> + priv->dma_regs = plat->dma_regs;
> +
> + /* init the zynq spi hw */
> + zynqmp_qspi_init_hw(priv);
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
what is the mode values your getting here? this mode is what platfdata
configured like what you did in above function.
see drivers/spi/stm32_qspi.c .set_mode
> +{
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> + struct zynqmp_qspi_regs *regs = priv->regs;
> + u32 confr;
> +
> + debug("%s\n", __func__);
> + /* Set the SPI Clock phase and polarities */
> + confr = readl(®s->confr);
> + confr &= ~(GQSPI_CONFIG_CPHA_MASK |
> + GQSPI_CONFIG_CPOL_MASK);
> +
> + if (priv->mode & SPI_CPHA)
> + confr |= GQSPI_CONFIG_CPHA_MASK;
> + if (priv->mode & SPI_CPOL)
> + confr |= GQSPI_CONFIG_CPOL_MASK;
> +
> + priv->mode = mode;
> + writel(confr, ®s->confr);
> +
> + debug("regs=%p, mode=%d\n", priv->regs, priv->mode);
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
> +{
> + u32 data;
> + int ret = 0;
> + struct zynqmp_qspi_regs *regs = priv->regs;
> + u32 *buf = (u32 *)priv->tx_buf;
> + u32 len = size;
> +
> + debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
> + size);
> +
> + while (size) {
> + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
> + GQSPI_TIMEOUT, 1);
> + if (ret) {
> + printf("%s: Timeout\n", __func__);
> + return ret;
> + }
> +
> + if (size >= 4) {
> + writel(*buf, ®s->txd0r);
> + buf++;
> + size -= 4;
> + } else {
> + switch (size) {
> + case 1:
> + data = *((u8 *)buf);
> + buf += 1;
> + data |= 0xFFFFFF00;
> + break;
> + case 2:
> + data = *((u16 *)buf);
> + buf += 2;
> + data |= 0xFFFF0000;
> + break;
> + case 3:
> + data = *((u16 *)buf);
> + buf += 2;
> + data |= (*((u8 *)buf) << 16);
> + buf += 1;
> + data |= 0xFF000000;
Use GENMASK instead of hexcodes.
> + break;
> + }
> + writel(data, ®s->txd0r);
> + size = 0;
> + }
> + }
> +
> + priv->tx_buf += len;
> + return 0;
> +}
> +
> +static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
> +{
> + u8 command = 1;
> + u32 gen_fifo_cmd;
> + u32 bytecount = 0;
> +
> + while (priv->len) {
> + gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> + gen_fifo_cmd |= GQSPI_GFIFO_TX;
> +
> + if (command) {
> + command = 0;
> + last_cmd = *(u8 *)priv->tx_buf;
> + }
don't understand this code can you explain? command assigned 1 it will
not updated anywhere?
> +
> + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> + gen_fifo_cmd |= *(u8 *)priv->tx_buf;
> + bytecount++;
> + priv->len--;
> + priv->tx_buf = (u8 *)priv->tx_buf + 1;
> +
> + debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
> +
> + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
> + }
> +}
> +
> +static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
> + u32 *gen_fifo_cmd)
> +{
> + u32 expval = 8;
> + u32 len;
> +
> + while (1) {
> + if (priv->len > 255) {
what is 255 here?
> + if (priv->len & (1 << expval)) {
> + *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
> + *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
> + *gen_fifo_cmd |= expval;
> + priv->len -= (1 << expval);
> + return expval;
> + }
> + expval++;
> + } else {
> + *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
> + GQSPI_GFIFO_EXP_MASK);
> + *gen_fifo_cmd |= (u8)priv->len;
> + len = (u8)priv->len;
> + priv->len = 0;
> + return len;
> + }
> + }
> +}
> +
> +static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
> +{
> + u32 gen_fifo_cmd;
> + u32 len;
> + int ret = 0;
> +
> + gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> + gen_fifo_cmd |= GQSPI_GFIFO_TX |
> + GQSPI_GFIFO_DATA_XFR_MASK;
> +
> + if (last_cmd == QUAD_PAGE_PROGRAM_CMD)
> + gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI;
> + else
> + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> +
> + while (priv->len) {
> + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
> + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
> +
> + debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
> +
> + if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
> + ret = zynqmp_qspi_fill_tx_fifo(priv,
> + 1 << len);
> + else
> + ret = zynqmp_qspi_fill_tx_fifo(priv,
> + len);
> +
> + if (ret)
> + return ret;
> + }
> + return ret;
> +}
> +
> +static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
> + u32 gen_fifo_cmd, u32 *buf)
> +{
> + u32 addr;
> + u32 size, len;
> + u32 actuallen = priv->len;
> + int ret = 0;
> + struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
> +
> + writel((unsigned long)buf, &dma_regs->dmadst);
> + writel(roundup(priv->len, 4), &dma_regs->dmasize);
> + writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
> + addr = (unsigned long)buf;
> + size = roundup(priv->len, ARCH_DMA_MINALIGN);
> + flush_dcache_range(addr, addr + size);
> +
> + while (priv->len) {
> + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
> + if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
> + (len % 4)) {
> + gen_fifo_cmd &= ~(0xFF);
> + gen_fifo_cmd |= (len / 4 + 1) * 4;
Need macros for these numerics
> + }
> + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
> +
> + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
> + }
> +
> + ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
> + 1, GQSPI_TIMEOUT, 1);
> + if (ret) {
> + printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
> + return -1;
> + }
> +
> + writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
> +
> + debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
> + (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
> + actuallen);
> +
> + if (buf != priv->rx_buf)
> + memcpy(priv->rx_buf, buf, actuallen);
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
> +{
> + u32 gen_fifo_cmd;
> + u32 *buf;
> + u32 actuallen = priv->len;
> +
> + gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> + gen_fifo_cmd |= GQSPI_GFIFO_RX |
> + GQSPI_GFIFO_DATA_XFR_MASK;
> +
> + if (last_cmd == QUAD_OUT_READ_CMD)
> + gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI;
> + else if (last_cmd == DUAL_OUTPUT_FASTRD_CMD)
> + gen_fifo_cmd |= GQSPI_SPI_MODE_DUAL_SPI;
> + else
> + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> +
> + /*
> + * Check if receive buffer is aligned to 4 byte and length
> + * is multiples of four byte as we are using dma to receive.
> + */
> + if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
> + !(actuallen % GQSPI_DMA_ALIGN)) {
> + buf = (u32 *)priv->rx_buf;
> + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
> + }
> +
> + ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
> + GQSPI_DMA_ALIGN));
> + buf = (u32 *)tmp;
> + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
> +}
> +
> +static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
> +{
> + int ret = 0;
> +
> + if (priv->is_inst) {
> + if (priv->tx_buf)
> + zynqmp_qspi_genfifo_cmd(priv);
> + else
> + ret = -1;
> + } else {
> + if (priv->tx_buf)
> + ret = zynqmp_qspi_genfifo_fill_tx(priv);
> + else if (priv->rx_buf)
> + ret = zynqmp_qspi_genfifo_fill_rx(priv);
> + else
> + ret = -1;
> + }
> + return ret;
> +}
> +
> +static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
> +{
> + static unsigned int cs_change = 1;
> + int status = 0;
> +
> + debug("%s\n", __func__);
> +
> + while (1) {
> + /* Select the chip if required */
> + if (cs_change)
> + zynqmp_qspi_chipselect(priv, 1);
> +
> + cs_change = priv->cs_change;
> +
> + if (!priv->tx_buf && !priv->rx_buf && priv->len) {
> + status = -1;
> + break;
> + }
> +
> + /* Request the transfer */
> + if (priv->len) {
> + status = zynqmp_qspi_start_transfer(priv);
> + priv->is_inst = 0;
> + if (status < 0)
> + break;
> + }
> +
> + if (cs_change)
> + /* Deselect the chip */
> + zynqmp_qspi_chipselect(priv, 0);
> + break;
> + }
> +
> + return status;
> +}
> +
> +static int zynqmp_qspi_claim_bus(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> + struct zynqmp_qspi_regs *regs = priv->regs;
> +
> + debug("%s\n", __func__);
drop this.
> + writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
> +
> + return 0;
> +}
> +
> +static int zynqmp_qspi_release_bus(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;
> + struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> + struct zynqmp_qspi_regs *regs = priv->regs;
> +
> + debug("%s\n", __func__);
drop this.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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