On 30.04.18 09:37, Michal Simek wrote:
> Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
> This patch is adding minimal support to get U-Boot boot.
> U-Boot on R5 runs out of DDR with default configuration that's why
> DDR needs to be partitioned if there is something else running on arm64.
> Console is done via Cadence uart driver and the first Cadence Triple
> Timer Counter is used for time.
>
> This configuration with uart1 was tested on zcu100-revC.
>
> U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
>
> Model: Xilinx ZynqMP R5
> DRAM: 512 MiB
> WARNING: Caches not enabled
> MMC:
> In: serial@ff010000
> Out: serial@ff010000
> Err: serial@ff010000
> Net: Net Initialization Skipped
> No ethernet found.
> ZynqMP r5>
>
> There are two ways how to run this on ZynqMP.
> 1. Run from ZynqMP arm64
> tftpb 20000000 u-boot-r5.elf
> setenv autostart no && bootelf -p 20000000
> cpu 4 disable && cpu 4 release 10000000 lockstep
> or
> cpu 4 disable && cpu 4 release 10000000 split
>
> 2. Load via jtag when directly to R5
>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
> ---
>
> Changes in v2:
> - Make this a single patch because core support was handled by Lokesh
> Vulta R5 series. Rebase on the top of this series
> - Add reset_cpu which is not handle by core
> - Add MPU support to enable only 0-512MB and RO for 512MB-2GB
> - Enable cache support
> - Wire MTEST macros but not enable mtest command
>
> Changes compare to RFC
> - Use 500MHz instead of 600MHz
> - Remove fpu compilation flags
> - Split arm-r5 code and platform
>
> ---
> MAINTAINERS | 6 +++
> arch/arm/Kconfig | 10 ++++
> arch/arm/Makefile | 1 +
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/zynqmp-r5.dts | 73 ++++++++++++++++++++++++++++++
> arch/arm/mach-zynqmp-r5/Kconfig | 27 +++++++++++
> arch/arm/mach-zynqmp-r5/Makefile | 3 ++
> arch/arm/mach-zynqmp-r5/cpu.c | 37 +++++++++++++++
> board/xilinx/zynqmp_r5/MAINTAINERS | 7 +++
> board/xilinx/zynqmp_r5/Makefile | 6 +++
> board/xilinx/zynqmp_r5/board.c | 25 ++++++++++
> configs/xilinx_zynqmp_r5_defconfig | 16 +++++++
> drivers/serial/Kconfig | 2 +-
> include/configs/xilinx_zynqmp_r5.h | 51 +++++++++++++++++++++
> 14 files changed, 265 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/zynqmp-r5.dts
> create mode 100644 arch/arm/mach-zynqmp-r5/Kconfig
> create mode 100644 arch/arm/mach-zynqmp-r5/Makefile
> create mode 100644 arch/arm/mach-zynqmp-r5/cpu.c
> create mode 100644 board/xilinx/zynqmp_r5/MAINTAINERS
> create mode 100644 board/xilinx/zynqmp_r5/Makefile
> create mode 100644 board/xilinx/zynqmp_r5/board.c
> create mode 100644 configs/xilinx_zynqmp_r5_defconfig
> create mode 100644 include/configs/xilinx_zynqmp_r5.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 147551f66fd3..e60d76dbad8a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -295,6 +295,12 @@ F: include/zynqmppl.h
> F: tools/zynqimage.c
> N: zynqmp
>
> +ARM ZYNQMP R5
> +M: Michal Simek <michal.si...@xilinx.com>
> +S: Maintained
> +T: git git://git.denx.de/u-boot-microblaze.git
> +F: arch/arm/mach-zynqmp-r5/
> +
> BUILDMAN
> M: Simon Glass <s...@chromium.org>
> S: Maintained
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f07f17f053ff..13e06ff763d0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -823,6 +823,14 @@ config ARCH_ZYNQ
> imply CMD_SPL
> imply ARCH_EARLY_INIT_R
>
> +config ARCH_ZYNQMP_R5
> + bool "Xilinx ZynqMP R5 based platform"
> + select CPU_V7R
> + select OF_CONTROL
> + select DM
> + select DM_SERIAL
> + select CLK
> +
> config ARCH_ZYNQMP
> bool "Xilinx ZynqMP based platform"
> select ARM64
> @@ -1345,6 +1353,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
>
> source "arch/arm/mach-zynq/Kconfig"
>
> +source "arch/arm/mach-zynqmp-r5/Kconfig"
> +
> source "arch/arm/cpu/armv7/Kconfig"
>
> source "arch/arm/cpu/armv8/zynqmp/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 3f5343bc017b..63e2b89ee7ef 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -78,6 +78,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp
> machine-$(CONFIG_TEGRA) += tegra
> machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
> machine-$(CONFIG_ARCH_ZYNQ) += zynq
> +machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
>
> machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1fb36b3ecdb3..d44a4310081e 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -165,6 +165,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
> zynqmp-zc1751-xm017-dc3.dtb \
> zynqmp-zc1751-xm018-dc4.dtb \
> zynqmp-zc1751-xm019-dc5.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
> + zynqmp-r5.dtb
> dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
> am335x-draco.dtb \
> am335x-evm.dtb \
> diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts
> new file mode 100644
> index 000000000000..a72172ef2ea4
> --- /dev/null
> +++ b/arch/arm/dts/zynqmp-r5.dts
> @@ -0,0 +1,73 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Xilinx ZynqMP R5
> + *
> + * (C) Copyright 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.si...@xilinx.com>
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "xlnx,zynqmp-r5";
> + model = "Xilinx ZynqMP R5";
> +
> + cpus {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-r5";
> + device_type = "cpu";
> + reg = <0>;
> + };
> + };
> +
> + aliases {
> + serial0 = &uart1;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + chosen {
> + bootargs = "";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + clk100: clk100 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + u-boot,dm-pre-reloc;
> + };
> +
> + amba {
> + u-boot,dm-pre-reloc;
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + ttc0: timer@ff110000 {
> + compatible = "cdns,ttc";
> + status = "okay";
> + reg = <0xff110000 0x1000>;
> + timer-width = <32>;
> + clocks = <&clk100>;
> + };
> +
> + uart1: serial@ff010000 {
> + u-boot,dm-pre-reloc;
> + compatible = "cdns,uart-r1p12", "xlnx,xuartps";
> + reg = <0xff010000 0x1000>;
> + clock-names = "uart_clk", "pclk";
> + clocks = <&clk100 &clk100>;
> + };
> + };
> +};
> diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig
> new file mode 100644
> index 000000000000..5e0175413395
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp-r5/Kconfig
> @@ -0,0 +1,27 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +if ARCH_ZYNQMP_R5
> +
> +config SYS_BOARD
> + string "Board name"
> + default "zynqmp_r5"
> +
> +config SYS_VENDOR
> + string "Vendor name"
> + default "xilinx"
> +
> +config SYS_SOC
> + default "zynqmp-r5"
> +
> +config SYS_CONFIG_NAME
> + string "Board configuration name"
> + default "xilinx_zynqmp_r5"
> + help
> + This option contains information about board configuration name.
> + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
> + will be used for board configuration.
> +
> +config SYS_MALLOC_F_LEN
> + default 0x600
> +
> +endif
> diff --git a/arch/arm/mach-zynqmp-r5/Makefile
> b/arch/arm/mach-zynqmp-r5/Makefile
> new file mode 100644
> index 000000000000..0d39e97dd371
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp-r5/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += cpu.o
> diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c
> new file mode 100644
> index 000000000000..4e855616b319
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp-r5/cpu.c
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
> + */
> +
> +#include <common.h>
> +#include <asm/armv7m_mpu.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct mpu_region_config region_config[] = {
> + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
> + O_I_WB_RD_WR_ALLOC, REGION_1GB },
> + { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
> + O_I_WB_RD_WR_ALLOC, REGION_512MB },
> + { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
> + O_I_WB_RD_WR_ALLOC, REGION_1GB },
> +};
> +
> +int arch_cpu_init(void)
> +{
> + gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
> +
> + setup_mpu_regions(region_config, sizeof(region_config) /
> + sizeof(struct mpu_region_config));
> +
> + return 0;
> +}
> +
> +/*
> + * Perform the low-level reset.
> + */
> +void reset_cpu(ulong addr)
> +{
> + while (1)
> + ;
> +}
> diff --git a/board/xilinx/zynqmp_r5/MAINTAINERS
> b/board/xilinx/zynqmp_r5/MAINTAINERS
> new file mode 100644
> index 000000000000..ac267649781a
> --- /dev/null
> +++ b/board/xilinx/zynqmp_r5/MAINTAINERS
> @@ -0,0 +1,7 @@
> +XILINX_ZYNQMP_R5 BOARDS
> +M: Michal Simek <michal.si...@xilinx.com>
> +S: Maintained
> +F: arch/arm/dts/zynqmp-r5*
> +F: board/xilinx/zynqmp_r5/
> +F: include/configs/xilinx_zynqmp_r5_*
> +F: configs/xilinx_zynqmp_r5_*
> diff --git a/board/xilinx/zynqmp_r5/Makefile b/board/xilinx/zynqmp_r5/Makefile
> new file mode 100644
> index 000000000000..c5a3e3d328bd
> --- /dev/null
> +++ b/board/xilinx/zynqmp_r5/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
> +#
> +
> +obj-y := board.o
> diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c
> new file mode 100644
> index 000000000000..70fb20235498
> --- /dev/null
> +++ b/board/xilinx/zynqmp_r5/board.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +
> +int board_init(void)
> +{
> + return 0;
> +}
> +
> +int dram_init_banksize(void)
> +{
> + return fdtdec_setup_memory_banksize();
> +}
> +
> +int dram_init(void)
> +{
> + if (fdtdec_setup_memory_size() != 0)
> + return -EINVAL;
> +
> + return 0;
> +}
> diff --git a/configs/xilinx_zynqmp_r5_defconfig
> b/configs/xilinx_zynqmp_r5_defconfig
> new file mode 100644
> index 000000000000..46715242e703
> --- /dev/null
> +++ b/configs/xilinx_zynqmp_r5_defconfig
> @@ -0,0 +1,16 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ZYNQMP_R5=y
> +CONFIG_SYS_TEXT_BASE=0x10000000
> +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
> +CONFIG_DEBUG_UART=y
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SYS_PROMPT="ZynqMP r5> "
> +# CONFIG_CMD_FLASH is not set
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_OF_EMBED=y
> +CONFIG_DEBUG_UART_ZYNQ=y
> +CONFIG_DEBUG_UART_BASE=0xff010000
> +CONFIG_DEBUG_UART_CLOCK=100000000
> +CONFIG_ZYNQ_SERIAL=y
> +CONFIG_TIMER=y
> +CONFIG_CADENCE_TTC_TIMER=y
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 4be8868536d8..5937910e5bf9 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -624,7 +624,7 @@ config STM32_SERIAL
>
> config ZYNQ_SERIAL
> bool "Cadence (Xilinx Zynq) UART support"
> - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
> + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP ||
> ARCH_ZYNQMP_R5)
> help
> This driver supports the Cadence UART. It is found e.g. in Xilinx
> Zynq/ZynqMP.
> diff --git a/include/configs/xilinx_zynqmp_r5.h
> b/include/configs/xilinx_zynqmp_r5.h
> new file mode 100644
> index 000000000000..05105e5d44e8
> --- /dev/null
> +++ b/include/configs/xilinx_zynqmp_r5.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
> + */
> +
> +#ifndef __CONFIG_ZYNQMP_R5_H
> +#define __CONFIG_ZYNQMP_R5_H
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS
> +
> +/* CPU clock */
> +#define CONFIG_CPU_FREQ_HZ 500000000
> +
> +/* Serial drivers */
> +/* The following table includes the supported baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
> +
> +# define CONFIG_ENV_SIZE (128 << 10)
> +
> +/* Allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/* Boot configuration */
> +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
> +
> +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
> +
> +#define CONFIG_NR_DRAM_BANKS 1
Is this enough? I would assume people will want to at least cover TCM
and DDR from within U-Boot.
The rest looks great to me :).
Alex
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