Hi Tom, please pull these fixes to your tree.
Here is travis session https://travis-ci.org/michalsimek/u-boot/builds/370046582 Thanks, Michal The following changes since commit 275d80a4c2fb63890f3f4c16b7ad481064e650a0: Merge git://git.denx.de/u-boot-usb (2018-04-22 09:30:36 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.05-rc3 for you to fetch changes up to ebc675b98d92f7b8264ca84e65cc896d95f9868b: cmd: clk: Check return value from soc_clk_dump (2018-04-23 13:15:32 +0200) ---------------------------------------------------------------- Xilinx fixes for v2018.05-rc3 - Fix nand initialization - Runtime ddr detection for static DDR setting - Enable rewriting env locations - Sync defconfig for zc770 xm011 - Remove useless ioremap in watchdog - Check return value from soc_clk_dump() ---------------------------------------------------------------- Ezequiel Garcia (2): nand: zynq: Fix driver initialization nand: zynq: Cleanup initialization Michal Simek (6): arm: zynq: Enable setup board name for different boards arm: zynq: Wire automatic ddr detection for Zynq and ZynqMP case arm: zynq: Make ENV_SIZE and ENV_OFFSET optional via board file arm: zynq: Sync zc770 xm011 defconfigs watchdog: cadence: Remove useless ioremap cmd: clk: Check return value from soc_clk_dump arch/arm/mach-zynq/Kconfig | 1 + arch/arm/mach-zynq/include/mach/nand.h | 9 --------- board/xilinx/zynq/board.c | 3 ++- board/xilinx/zynqmp/zynqmp.c | 3 ++- cmd/clk.c | 10 +++++++++- configs/zynq_zc770_xm011_x16_defconfig | 2 +- drivers/mtd/nand/zynq_nand.c | 8 +++----- drivers/watchdog/cdns_wdt.c | 5 ----- include/configs/zynq-common.h | 8 ++++++-- 9 files changed, 24 insertions(+), 25 deletions(-) delete mode 100644 arch/arm/mach-zynq/include/mach/nand.h -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs
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