Hello, In arch/arm/include/asm/mach-imx/iomux-v3.h you find defines of PAD_CTL_SPEED_*. For the i.MX 6 SX, i.MX 6 UL, and the i.MX 6 ULL the PAD_CTL_SPEED_LOW field is set to 0. For all other i.MX6 processors it will be 1. I compared that to the definition found in the i.MX 6Solo/6DualLite Application Processor Reference Manual, Rev. 3, Page 2646 [1] for the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register. I found that the i.MX 6 S and i.MX 6 DL the PAD_CTL_SPEED_LOW field shall be 0, too.
I then checked more Reference Manuals (RM) looking at the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK or IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 register and found the following. i.MX 6 Solo RM [1]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 DualLite RM [1]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 Dual RM [2]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 Quad RM [2]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 SoloLite RM [3]: 00 RESERVED, 01 Low, 10 Medium, 11 Maximum i.MX 6 SoloX RM [4]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 DualPlus RM [5]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 QuadPlus RM [5]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 ULL RM [6]: 00 Low, 01 Medium, 10 Medium, 11 Maximum i.MX 6 UltraLite RM: only available under a licensing agreement Combining the knowledge from the RMs above and the existing code, it seems that only the SoloLite is different. Thus, I propose the attached patch. Greetings, Mark [1] https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf [2] https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf [3] https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf [4] https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf [5] https://www.nxp.com/docs/en/reference-manual/iMX6DQPRM.pdf [6] https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf
0001-arm-imx6-fix-PAD_CTL_SPEED_LOW-constant.patch
Description: 0001-arm-imx6-fix-PAD_CTL_SPEED_LOW-constant.patch
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