This patch adds support for the gigabit interface found on the Allwinner R40/V40 CPU. It does not support the 100Mbit interface (EMAC).
Fixes: - add GMAC gating clock and reset control - GPIO mux settings - device tree entries Tested on BananaPi M2 Berry (R40), custom board (V40). Signed-off-by: Lothar Felten <lothar.fel...@gmail.com> --- arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++ arch/arm/dts/sun8i-r40.dtsi | 37 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++- board/sunxi/gmac.c | 5 +++- configs/Bananapi_M2_Ultra_defconfig | 4 +++ drivers/net/sun8i_emac.c | 2 ++ 6 files changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index ab471ab0bf..25f2112fbf 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -67,3 +67,17 @@ pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii>; + status = "okay"; + phy-handle = <&rgmii_phy>; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 48ec2e855a..93bf811014 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -114,6 +114,12 @@ #size-cells = <1>; ranges; + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-r40-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; @@ -126,6 +132,15 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + gmac_pins_rgmii: gmac_rgmii { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + function = "gmac"; + }; + i2c0_pins: i2c0_pins { pins = "PB0", "PB1"; function = "i2c0"; @@ -159,6 +174,28 @@ #size-cells = <0>; }; + gmac: ethernet@01c50000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c50000 0x2000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&osc24M>, <&osc24M>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii>; + phy-mode = "rgmii"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d35aa479f7..5af8c64fa2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -61,7 +61,11 @@ struct sunxi_ccm_reg { u32 reserved11; u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ u32 usb_clk_cfg; /* 0xcc USB clock control */ - u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ +#ifndef CONFIG_MACH_SUN8I_R40 + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */ +#else + u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */ +#endif u32 reserved12[7]; u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ @@ -104,7 +108,11 @@ struct sunxi_ccm_reg { u32 mtc_clk_cfg; /* 0x158 MTC module clock */ u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ +#ifndef CONFIG_MACH_SUN8I_R40 u32 reserved16; +#else + u32 gmac_clk_cfg; /* 0x164 GMAC clock control (only R40) */ +#endif u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ u32 reserved17[4]; diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 826650c89b..b2ede37dc3 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -13,7 +13,10 @@ void eth_init_board(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I +#if defined(CONFIG_MACH_SUN8I_R40) + setbits_le32(&ccm->ahb_reset1_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#elif defined(CONFIG_SUNXI_GEN_SUN6I) setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); #else diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 37cc2df5dc..e4e943dc49 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -17,3 +17,7 @@ CONFIG_AXP_DLDO4_VOLT=2500 CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_SUN8I_EMAC=y +CONFIG_RGMII=y +CONFIG_SUN7I_GMAC=y +CONFIG_MACPWR="PA17" diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index b6e5dafe83..0cb1a697f3 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -68,6 +68,8 @@ #if defined(CONFIG_MACH_SUNXI_H3_H5) #define SUN8I_GPD8_GMAC 2 +#elif defined(CONFIG_MACH_SUN8I_R40) +#define SUN8I_GPD8_GMAC 5 #else #define SUN8I_GPD8_GMAC 4 #endif -- 2.14.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot