Hello Nick. > On TI DA830, the 1.0 & 1.1 revision of the silicon have a data caching > bug. You can use data caching, but only in write thru' mode.
I see. So instead of both C and B you just need to C bit set in the page table, and no B. I propose to allow an extra option for write-back, leaving write-through as the default. This matches the blackfin, which has CONFIG_DCACHE_WB as an option, and leaves a safer default for those who won't explicitly require WB policy. Could you please confirm my patch works on that board after changing the magic bits from 0x1e to 0x1a ? (I'll use symbolic constants anyways in V2, this was just a quick RFC to see if the approach is acceptable). /alessandro _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
