As per the IFC hardware manual, Most significant 2 bytes in
nand_fsr register are the outcome of NAND READ STATUS command.
So status value need to be shifted and aligned as per the nand
framework requirement.
Signed-off-by: Jagdish Gediya <jagdish.ged...@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
---
drivers/mtd/nand/fsl_ifc_nand.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 34016cb..e34eb3d 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -725,10 +725,11 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct
nand_chip *chip)
return NAND_STATUS_FAIL;
nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
+ nand_fsr >>= 16;
+ nand_fsr = (nand_fsr >> 8) | (nand_fsr << 8);
/* Chip sometimes reporting write protect even when it's not */
- nand_fsr = nand_fsr | NAND_STATUS_WP;
- return nand_fsr;
+ return (nand_fsr & 0xff) | NAND_STATUS_WP;
}
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
--
1.9.1
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