On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.john...@nxp.com> wrote:
> This patch enables ethernet support for ls1012aqds.
>
> Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
> ---
> Changes in v2:
> -split from original patch "board: freescale: ls1012a: enable network
> support on ls1012a platforms"
> ---
> board/freescale/ls1012aqds/Kconfig | 14 ++
> board/freescale/ls1012aqds/Makefile | 1 +
> board/freescale/ls1012aqds/eth.c | 304
> ++++++++++++++++++++++++++
> board/freescale/ls1012aqds/ls1012aqds.c | 97 +++++++-
> board/freescale/ls1012aqds/ls1012aqds_pfe.h | 48 ++++
> board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
> 6 files changed, 459 insertions(+), 7 deletions(-)
> create mode 100644 board/freescale/ls1012aqds/eth.c
> create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
>
[ ... ]
> diff --git a/board/freescale/ls1012aqds/eth.c
> b/board/freescale/ls1012aqds/eth.c
> new file mode 100644
> index 0000000..41d077a
> --- /dev/null
> +++ b/board/freescale/ls1012aqds/eth.c
[ ... ]
> +int pfe_eth_board_init(struct udevice *dev)
> +{
> + static int init_done;
> + struct mii_dev *bus;
> + static const char *mdio_name;
> + struct pfe_mdio_info mac_mdio_info;
> + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
> + u8 data8;
> + struct pfe_eth_dev *priv = dev_get_priv(dev);
> +
> + int srds_s1 = in_be32(&gur->rcwsr[4]) &
> + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
> + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
> +
> + ls1012aqds_mux_mdio(EMI1_SLOT1);
> +
> + if (!init_done) {
> + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
> + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
> +
> + bus = pfe_mdio_init(&mac_mdio_info);
> + if (!bus) {
> + printf("Failed to register mdio\n");
> + return -1;
> + }
> + init_done = 1;
> + }
> +
> + if (priv->gemac_port) {
> + mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
> + mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
> +
> + bus = pfe_mdio_init(&mac_mdio_info);
> + if (!bus) {
> + printf("Failed to register mdio\n");
> + return -1;
> + }
> + }
> +
> + switch (srds_s1) {
> + case 0x3508:
> + printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
> +#ifdef RGMII_RESET_WA
> + /* Work around for FPGA registers initialization
Please use the normal multi-line comment style where the first /* stands alone.
> + * This is needed for RGMII to work.
> + */
> + printf("Reset RGMII WA....\n");
> + data8 = QIXIS_READ(rst_frc[0]);
> + data8 |= 0x2;
> + QIXIS_WRITE(rst_frc[0], data8);
> + data8 = QIXIS_READ(rst_frc[0]);
> +
> + data8 = QIXIS_READ(res8[6]);
> + data8 |= 0xff;
> + QIXIS_WRITE(res8[6], data8);
> + data8 = QIXIS_READ(res8[6]);
> +#endif
[ ... ]
> diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h
> b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
> new file mode 100644
> index 0000000..c279ef3
> --- /dev/null
> +++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#define ETH_1_1G_BUS_ID 0x1
> +#define ETH_1_1G_PHY_ID 0x1e
> +#define ETH_1_1G_MDIO_MUX 0x2
> +#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD
> +#define ETH_1_1G_PHY_MODE "sgmii"
> +#define ETH_2_1G_BUS_ID 0x1
> +#define ETH_2_1G_PHY_ID 0x1
> +#define ETH_2_1G_MDIO_MUX 0x1
> +#define ETH_2_1G_PHY_MODE "rgmii"
> +
> +#define ETH_1_2_5G_BUS_ID 0x0
> +#define ETH_1_2_5G_PHY_ID 0x1
> +#define ETH_1_2_5G_MDIO_MUX 0x2
> +#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
> +#define ETH_2_5G_PHY_MODE "sgmii-2500"
> +#define ETH_2_2_5G_BUS_ID 0x1
> +#define ETH_2_2_5G_PHY_ID 0x2
> +#define ETH_2_2_5G_MDIO_MUX 0x3
> +
> +#define SERDES_1_G_PROTOCOL 0x3508
> +#define SERDES_2_5_G_PROTOCOL 0x2205
> +
> +#define PFE_PROP_LEN 4
> +
> +#define ETH_1_SOC_PATH "/soc/pfe@04000000/ethernet@0"
> +#define ETH_1_PATH "/pfe@04000000/ethernet@0"
> +#define ETH_2_SOC_PATH "/soc/pfe@04000000/ethernet@1"
> +#define ETH_2_PATH "/pfe@04000000/ethernet@1"
Seems like you could easily define *_SOC_PATH in terms of *_PATH
like:
#define ETH_1_PATH "/pfe@04000000/ethernet@0"
#define ETH_1_SOC_PATH "/soc" ETH_1_PATH
> +
> +#define ETH_1_MDIO_SOC_PATH "/soc/pfe@04000000/ethernet@0/mdio@0"
> +#define ETH_1_MDIO "/pfe@04000000/ethernet@0/mdio@0"
> +#define ETH_2_MDIO_SOC_PATH "/soc/pfe@04000000/ethernet@1/mdio@0"
> +#define ETH_2_MDIO "/pfe@04000000/ethernet@1/mdio@0"
> +
> +#define NUM_ETH_NODE 2
> +struct pfe_prop_val {
> + int busid;
> + int phyid;
> + int mux_val;
> + int phy_mask;
> + char *phy_mode;
> +};
> diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> index 584f604..7a1ba3d 100644
> --- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> @@ -11,7 +11,7 @@
>
> /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
> #define BRDCFG4_EMISEL_MASK 0xe0
> -#define BRDCFG4_EMISEL_SHIFT 5
> +#define BRDCFG4_EMISEL_SHIFT 6
>
> /* SYSCLK */
> #define QIXIS_SYSCLK_66 0x0
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
