I hadn't dug into it yet to find the polling behavior but like you said with no idle the CPU. It was just different behavior from what I see with the SD which is some CPU time spent waiting on I/O (maybe because of the DMA vs polling).
I did find a few of simple optimizations that gained me ~1MBs increase on NAND and SD as well. - /proc/sys/vm/dirty_expire_centiseconds = 2 - /proc/sys/vm/dirty_background_ratio = 5 - Unchecked KConfig "Optimize for size" which was enabled by default. Thanks for your feedback. Appareo Systems, LLC 1810 NDSU Research Circle N Fargo, ND 58102 JOSH GELINSKE FIRMWARE ENGINEERING MANAGER Appareo Systems, LLC 1810 NDSU Research Circle N Fargo, ND 58102 P: (701) 356-2200 Ext 251 C: (701) 306-0899 F: (701) 356-3157 http://www.appareo.com jgelin...@appareo.com NOTICE: This message (including attachments) is covered by the Electronic Communication Privacy Act, 18 U.S.C. sections 2510-2521, is CONFIDENTIAL and may also be protected by ATTORNEY-CLIENT OR OTHER PRIVILEGE. If you believe that it has been sent to you in error, do not read it. If you are not the intended recipient, you are hereby notified that any retention, dissemination, distribution, or copying of this communication is strictly prohibited. Please reply to the sender that you have received the message in error and then delete it. -----Original Message----- From: Nick Thompson [mailto:nick.thomp...@ge.com] Sent: Monday, January 18, 2010 6:48 AM To: Josh Gelinske Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH RFC] NAND: Improve read performance from Large Page NAND devices On 16/01/10 01:51, Josh Gelinske wrote: > > What kind of CPU usage are you seeing? I am throughput of ~1.9MBs for writes > on a Samsung K9WBG08U1M 4GB with 4K page but with high cpu usage. > I'm not sure what you are asking here. There is no idle loop to measure so CPU is running at 100%. The code does poll the NAND device for data ready, but in my case the NAND loads its cache faster than the CPU can finish sorting out ECC checks (despite ECC H/W assistance). The result is the CPU never actually on the NAND. This patch (not yet formally submitted) removes this potential waiting time that was present - plus some redundant command sequences due to incorrect function levelling. Most of my performance gain comes from optimising the data transfer (to and) from the NAND - see drivers/mtd/nand/davinci_nand.c - which is already in the mainline. Apologies if that doesn't answer your question. Nick. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
