Extract the macros specific to Gen3 clock into a separate header.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
drivers/clk/renesas/rcar-gen3-cpg.h | 60 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.h | 41 ----------------------
6 files changed, 64 insertions(+), 41 deletions(-)
create mode 100644 drivers/clk/renesas/rcar-gen3-cpg.h
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 144d9becd9..c5d22f55d4 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -18,6 +18,7 @@
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 016ab3dc28..80e07dacce 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -18,6 +18,7 @@
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c
b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index 782ea25262..5a031cb6eb 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -18,6 +18,7 @@
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 2e07cb2768..f4b0699f33 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -18,6 +18,7 @@
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
new file mode 100644
index 0000000000..2f410df42a
--- /dev/null
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -0,0 +1,60 @@
+/*
+ * R-Car Gen3 Clock Pulse Generator
+ *
+ * Copyright (C) 2015-2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
+#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
+
+enum rcar_gen3_clk_types {
+ CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
+ CLK_TYPE_GEN3_PLL0,
+ CLK_TYPE_GEN3_PLL1,
+ CLK_TYPE_GEN3_PLL2,
+ CLK_TYPE_GEN3_PLL3,
+ CLK_TYPE_GEN3_PLL4,
+ CLK_TYPE_GEN3_SD,
+ CLK_TYPE_GEN3_RPC,
+ CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_Z2,
+};
+
+#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
+
+struct rcar_gen3_cpg_pll_config {
+ u8 extal_div;
+ u8 pll1_mult;
+ u8 pll1_div;
+ u8 pll3_mult;
+ u8 pll3_div;
+};
+
+#define CPG_RCKCR 0x240
+
+struct gen3_clk_priv {
+ void __iomem *base;
+ struct cpg_mssr_info *info;
+ struct clk clk_extal;
+ struct clk clk_extalr;
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+};
+
+int gen3_clk_probe(struct udevice *dev);
+int gen3_clk_remove(struct udevice *dev);
+
+extern const struct clk_ops gen3_clk_ops;
+
+#endif
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index eee8b8f5cb..c0c6ae224e 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -29,14 +29,6 @@ struct cpg_mssr_info {
const void *(*get_pll_config)(const u32 cpg_mode);
};
-struct gen3_clk_priv {
- void __iomem *base;
- struct cpg_mssr_info *info;
- struct clk clk_extal;
- struct clk clk_extalr;
- const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
-};
-
/*
* Definitions of CPG Core Clocks
*
@@ -75,14 +67,6 @@ enum clk_types {
DEF_TYPE(_name, _id, CLK_TYPE_IN)
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
-#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
-#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
- _div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, \
- (_parent_clean), .div = (_div_clean), 1)
/*
* Definitions of Module Clocks
@@ -101,26 +85,6 @@ struct mssr_mod_clk {
#define DEF_MOD(_name, _mod, _parent...) \
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
-enum rcar_gen3_clk_types {
- CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
- CLK_TYPE_GEN3_PLL0,
- CLK_TYPE_GEN3_PLL1,
- CLK_TYPE_GEN3_PLL2,
- CLK_TYPE_GEN3_PLL3,
- CLK_TYPE_GEN3_PLL4,
- CLK_TYPE_GEN3_SD,
- CLK_TYPE_GEN3_RPC,
- CLK_TYPE_GEN3_R,
- CLK_TYPE_GEN3_PE,
- CLK_TYPE_GEN3_Z2,
-};
-
-struct rcar_gen3_cpg_pll_config {
- unsigned int extal_div;
- unsigned int pll1_mult;
- unsigned int pll3_mult;
-};
-
struct mstp_stop_table {
u32 dis;
u32 en;
@@ -129,9 +93,4 @@ struct mstp_stop_table {
#define TSTR0 0x04
#define TSTR0_STR0 BIT(0)
-int gen3_clk_probe(struct udevice *dev);
-int gen3_clk_remove(struct udevice *dev);
-
-extern const struct clk_ops gen3_clk_ops;
-
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
--
2.15.1
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