Hi Peng, On 23/01/2018 02:54, Peng Fan wrote: >> >> I guess we will not have any improvement here, at least for first version. > > I'll give a try to improve the ddr controller part. For ddr phy > part, it is impossible to do that, it was autogenerated by tool > from synopsys.
ok, I supposed something of this type - no human being will generate this mess :-). Anyway, this is fine if we can describe how it works. We have already such a case with Altera SOCFPGA: the Altera's tool generates headers for DDR and they are just imported into u-boot. Search for "qts" directories, for example ./board/altera/arria5-socdk/qts. But if these files are generated, we should also be sure that we do not need to change them in U-Boot: tool generates DDR files, and we import them in U-Boot. If tool produces them in another format such as a table, we just need a small converter (python, perl, ...) that translates the tables into C header / files (as we already do for assembly, for example). In this way the chain is not broken: synopsys generates the files, we import them into U-Boot and this becomes straightforward for board maintainers. Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
