On Tue, 9 Jan 2018 19:01:34 +0100 Hannes Schmelzer oe5...@oevsv.at wrote: > The LCDC IP-core an be feed from several clock sources, one of those is > a dedicated DPLL for generating a dividable base-clock for this IP-core. > > The TRM specifies the maximum input frequency for the LCCD with 200 MHz, > so we must not exceed this value with the PLL frequency (which can lock > much higher). > > This patch tries every combination of multipliers and divisors of the > PLL and the IP-core itself for getting as near as possible the the > requested panel->pxl_clk. > > Signed-off-by: Hannes Schmelzer <oe5...@oevsv.at>
Reviewed-by: Anatolij Gustschin <ag...@denx.de> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
