LS1012A-2G5RDB belongs to LS1012A family with features
1. 2 2.5G SGMII PFE Block
2. Sata
3. USB 2.0/3.0
4. WiFi
5. DDR
6. eMMC
7. QuadSPI
8. UART
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>
---
Depends on https://patchwork.ozlabs.org/cover/823205
arch/arm/Kconfig | 13 ++
arch/arm/cpu/armv8/Kconfig | 2 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1012a-2g5rdb.dts | 16 +++
arch/arm/dts/fsl-ls1012a-2g5rdb.dtsi | 39 ++++++
board/freescale/ls1012a2g5rdb/Kconfig | 17 +++
board/freescale/ls1012a2g5rdb/MAINTAINERS | 6 +
board/freescale/ls1012a2g5rdb/Makefile | 8 ++
board/freescale/ls1012a2g5rdb/README | 46 +++++++
board/freescale/ls1012a2g5rdb/eth.c | 62 +++++++++
board/freescale/ls1012a2g5rdb/ls1012a2g5rdb.c | 173 ++++++++++++++++++++++++++
configs/ls1012a2g5rdb_qspi_defconfig | 53 ++++++++
drivers/net/pfe_eth/pfe_eth.c | 37 +-----
include/configs/ls1012a2g5rdb.h | 82 ++++++++++++
14 files changed, 519 insertions(+), 36 deletions(-)
create mode 100644 arch/arm/dts/fsl-ls1012a-2g5rdb.dts
create mode 100644 arch/arm/dts/fsl-ls1012a-2g5rdb.dtsi
create mode 100644 board/freescale/ls1012a2g5rdb/Kconfig
create mode 100644 board/freescale/ls1012a2g5rdb/MAINTAINERS
create mode 100644 board/freescale/ls1012a2g5rdb/Makefile
create mode 100644 board/freescale/ls1012a2g5rdb/README
create mode 100644 board/freescale/ls1012a2g5rdb/eth.c
create mode 100644 board/freescale/ls1012a2g5rdb/ls1012a2g5rdb.c
create mode 100644 configs/ls1012a2g5rdb_qspi_defconfig
create mode 100644 include/configs/ls1012a2g5rdb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 94ad805..1c75810 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -932,6 +932,18 @@ config TARGET_LS1012ARDB
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012A2G5RDB
+ bool "Support ls1012a2g5rdb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ help
+ Support for Freescale LS1012A2G5RDB platform.
+ The LS1012A 2G5 Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A
@@ -1256,6 +1268,7 @@ source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012a2g5rdb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 12aba9d..3de2706 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -92,7 +92,7 @@ config PSCI_RESET
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
- !TARGET_LS2081ARDB && \
+ !TARGET_LS2081ARDB && !TARGET_LS1012A2G5RDB && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd540e9..0311d42 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -201,6 +201,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
new file mode 100644
index 0000000..304eedd
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-2g5rdb.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dtsi
b/arch/arm/dts/fsl-ls1012a-2g5rdb.dtsi
new file mode 100644
index 0000000..ac15670
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A 2G5 RDB Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/board/freescale/ls1012a2g5rdb/Kconfig
b/board/freescale/ls1012a2g5rdb/Kconfig
new file mode 100644
index 0000000..41c0606
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_LS1012A2G5RDB
+
+config SYS_BOARD
+ default "ls1012a2g5rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012a2g5rdb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1012a2g5rdb/MAINTAINERS
b/board/freescale/ls1012a2g5rdb/MAINTAINERS
new file mode 100644
index 0000000..04821ae
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012A2G5RDB BOARD
+M: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
+S: Maintained
+F: board/freescale/ls1012a2g5rdb/
+F: include/configs/ls1012a2g5rdb.h
+F: configs/ls1012a2g5rdb_qspi_defconfig
diff --git a/board/freescale/ls1012a2g5rdb/Makefile
b/board/freescale/ls1012a2g5rdb/Makefile
new file mode 100644
index 0000000..626e673
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012a2g5rdb.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012a2g5rdb/README
b/board/freescale/ls1012a2g5rdb/README
new file mode 100644
index 0000000..1e9b5c0
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/README
@@ -0,0 +1,46 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012A2G5RDB board Overview
+-----------------------
+ - SERDES Connections, 3 lanes supporting:
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - SDIO WiFi, SPI
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on 2G5RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash 1
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4030_0000
+PPA FIT image | 2MB | 0x4040_0000
+Linux ITB | ~53MB | 0x4100_0000
diff --git a/board/freescale/ls1012a2g5rdb/eth.c
b/board/freescale/ls1012a2g5rdb/eth.c
new file mode 100644
index 0000000..d200cb5
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/eth.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include <pfe_eth/pfe_eth.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <i2c.h>
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_PFE
+ struct mii_dev *bus;
+ struct mdio_info mac1_mdio_info;
+
+ init_pfe_scfg_dcfg_regs();
+
+ mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = ls1012a_mdio_init(&mac1_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+
+ mac1_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+ mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+ bus = ls1012a_mdio_init(&mac1_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio \n");
+ return -1;
+ }
+
+ /* MAC1 */
+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+
+ /* MAC2 */
+ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+
+ cpu_eth_init(bis);
+#endif
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1012a2g5rdb/ls1012a2g5rdb.c
b/board/freescale/ls1012a2g5rdb/ls1012a2g5rdb.c
new file mode 100644
index 0000000..7590167
--- /dev/null
+++ b/board/freescale/ls1012a2g5rdb/ls1012a2g5rdb.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+#include <fsl_sec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ u8 in1;
+
+ puts("Board: LS1012A2G5RDB ");
+
+ /* Initialize i2c early for Serial flash bank information */
+ i2c_set_bus_num(0);
+
+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ puts("Version");
+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+ puts(": RevA");
+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+ puts(": RevB");
+ else
+ puts(": unknown");
+
+ printf(", boot from QSPI");
+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+ puts(": emu\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+ puts(": bank1\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+ puts(": bank2\n");
+ else
+ puts("unknown\n");
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ static const struct fsl_mmdc_info mparam = {
+ 0x05180000, /* mdctl */
+ 0x00030035, /* mdpdc */
+ 0x12554000, /* mdotc */
+ 0xbabf7954, /* mdcfg0 */
+ 0xdb328f64, /* mdcfg1 */
+ 0x01ff00db, /* mdcfg2 */
+ 0x00001680, /* mdmisc */
+ 0x0f3c8000, /* mdref */
+ 0x00002000, /* mdrwd */
+ 0x00bf1023, /* mdor */
+ 0x0000003f, /* mdasp */
+ 0x0000022a, /* mpodtctrl */
+ 0xa1390003, /* mpzqhwctrl */
+ };
+
+ mmdc_init(&mparam);
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+ ppa_init();
+#endif
+ return 0;
+}
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ char esdhc0_path[] = "/soc/esdhc@1560000";
+ char esdhc1_path[] = "/soc/esdhc@1580000";
+ u8 io = 0;
+ u8 mux_sdhc2;
+
+ do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+ sizeof("okay"), 1);
+
+ i2c_set_bus_num(0);
+
+ /*
+ * The I2C IO-expander for mux select is used to control the muxing
+ * of various onboard interfaces.
+ *
+ * IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
+ * 00 - SDIO wifi
+ * 01 - GPIO (to Arduino)
+ * 10 - eMMC Memory
+ * 11 - SPI
+ */
+ if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ mux_sdhc2 = (io & 0x0c) >> 2;
+ /* Enable SDHC2 only when use SDIO wifi and eMMC */
+ if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+ do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+ sizeof("okay"), 1);
+ else
+ do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig
b/configs/ls1012a2g5rdb_qspi_defconfig
new file mode 100644
index 0000000..80193b3
--- /dev/null
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_FSL_PFE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index 4db823f..e98786a 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -381,11 +381,6 @@ struct mii_dev *ls1012a_mdio_init(struct mdio_info
*mdio_info)
static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
{
struct mii_dev bus;
- int value, sgmii_2500 = 0;
- struct gemac_s *gem = priv->gem;
-
- if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
- sgmii_2500 = 1;
printf("%s %d\n", __func__, priv->gemac_port);
@@ -396,37 +391,9 @@ static void ls1012a_configure_serdes(struct
ls1012a_eth_dev *priv)
ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
-
- /* Reset serdes */
ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
-
- /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
- value = PHY_SGMII_IF_MODE_SGMII;
- if (!sgmii_2500)
- value |= PHY_SGMII_IF_MODE_AN;
- else
- value |= PHY_SGMII_IF_MODE_SGMII_GBT;
-
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
-
- /* Dev ability according to SGMII specification */
- value = PHY_SGMII_DEV_ABILITY_SGMII;
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
-
- /* These values taken from validation team */
- if (!sgmii_2500) {
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
- } else {
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
- }
-
- /* Restart AN */
- value = PHY_SGMII_CR_DEF_VAL;
- if (!sgmii_2500)
- value |= PHY_SGMII_CR_RESET_AN;
- ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, 0x8);
+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8140);
}
void ls1012a_set_mdio(int dev_id, struct mii_dev *bus)
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
new file mode 100644
index 0000000..e8d389b
--- /dev/null
+++ b/include/configs/ls1012a2g5rdb.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A2G5RDB_H__
+#define __LS1012A2G5RDB_H__
+
+#include "ls1012a_common.h"
+
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x2
+#define EMAC2_PHY_ADDR 0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
+#endif
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR 0x24
+#define __SW_BOOT_MASK 0xFC
+#define __SW_BOOT_EMU 0x10
+#define __SW_BOOT_BANK1 0x00
+#define __SW_BOOT_BANK2 0x01
+#define __SW_REV_MASK 0x07
+#define __SW_REV_A 0xF8
+#define __SW_REV_B 0xF0
+
+#define I2C_MUX_IO2_ADDR 0x25
+#define __PHY_MASK 0xF9
+#define __PHY_ETH2_MASK 0xFB
+#define __PHY_ETH1_MASK 0xFD
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A2G5RDB_H__ */
--
1.9.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
