On 26.12.2009 19:40, Mike Frysinger wrote:
> On Friday 25 December 2009 13:57:55 Dirk Behme wrote:
>> I started to convert the enc28j60.c to common SPI framework. Do you
>> like to have a look at attachment (and maybe test it?)?
>>
>> It is compile tested only. And for the moment it just re-uses the
>> existing driver. When we know that it basically works this way, doing
>> it in a clean way as you describe above would be the next step.
>> CONFIG_NET_MULTI is still missing, too.
>
> spi_lock/spi_unlock should redirect to spi_claim_bus/spi_release_bus. this
> isnt so much an "interrupts" issue as the process of claiming the bus
> reprograms the controller with the slave settings.
>
>> In your config file you have to set and configure
>>
>> #define CONFIG_xxx_SPI
>> #define CONFIG_ENC28J60
>> #define CONFIG_ENC28J60_SPI_BUS 0
>> #define CONFIG_ENC28J60_SPI_CS 0
>> #define CONFIG_ENC28J60_SPI_CLK 1000000
>> #define CONFIG_CMD_NET
>>
>> for your board.
>
> this is ok with the current design, but broken for NET_MULTI. when converted
> to NET_MULTI, the new enc28j60_register() function will take the spi settings
> as function arguments. so the function would look something like:
> int enc28j60_register(bd_t *bis, unsigned int spi_bus, unsigned int spi_cs,
> unsigned int max_hz, unsigned int mode);
>
> and it'd be up to the board to call it with the settings it wants
Both changes, enc28j60_initialize() (NET_MULTI enabled) and
spi_claim_bus/spi_release_bus done in below.
In the the board file I now have
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_ENC28J60
rc = enc28j60_initialize(bis,
CONFIG_ENC28J60_SPI_BUS,
CONFIG_ENC28J60_SPI_CS,
CONFIG_ENC28J60_SPI_CLK,
SPI_MODE_3);
#endif
return rc;
}
Do you like to test? Any further comments?
As mentioned, when we know that it works this way, I will do a clean
version.
Best regards
Dirk
Index: u-boot-main/drivers/net/enc28j60.c
===================================================================
--- u-boot-main.orig/drivers/net/enc28j60.c
+++ u-boot-main/drivers/net/enc28j60.c
@@ -18,8 +18,8 @@
#include <config.h>
#include <common.h>
#include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
+//#include <asm/arch/hardware.h>
+#include <spi.h>
/*
* Control Registers in Bank 0
@@ -284,10 +284,14 @@
/* maximum frame length */
#define ENC_MAX_FRM_LEN 1518
-#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
-#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
-#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
-
+#define enc_enable(x) spi_cs_activate(x);
+#define enc_disable(x) spi_cs_deactivate(x);
+#define spi_write(x) spi_w8r8(slave, x)
+#define spi_read() spi_w8r8(slave, 0)
+#define spi_lock() spi_claim_bus(slave)
+#define spi_unlock() spi_release_bus(slave)
+/* Use spi_setup_slave() instead of enc_cfg_spi() */
+#define enc_cfg_spi()
static unsigned char encReadReg (unsigned char regNo);
static void encWriteReg (unsigned char regNo, unsigned char data);
@@ -322,25 +326,26 @@ static unsigned char next_pointer_msb;
static unsigned char buffer[ENC_MAX_FRM_LEN];
static int rxResetCounter = 0;
+static struct spi_slave *slave;
+
#define RX_RESET_COUNTER 1000;
/*-----------------------------------------------------------------------------
* Always returns 0
*/
-int eth_init (bd_t * bis)
+int enc28j60_initialize(bd_t *bis, unsigned int spi_bus, unsigned int
spi_cs,
+ unsigned int max_hz, unsigned int mode)
{
unsigned char estatVal;
uchar enetaddr[6];
- /* configure GPIO */
- (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
- (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
-
- /* CS and RESET active low */
- PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
- PUT32 (IO1SET, ENC_RESET);
-
spi_init ();
+ if (!slave) {
+ slave = spi_setup_slave(spi_bus, spi_cs, max_hz, mode);
+ if (!slave)
+ return -1;
+ }
+ spi_claim_bus(slave);
/* taken from the Linux driver - dangerous stuff here! */
/* Wait for CLKRDY to become set (i.e., check that we can
communicate with
@@ -592,17 +597,17 @@ static void encWriteReg (unsigned char r
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x40 | regNo); /* write in regNo */
spi_write (data);
- enc_disable ();
- enc_enable ();
+ enc_disable (slave);
+ enc_enable (slave);
spi_write (0x1f); /* write reg 0x1f */
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
}
@@ -615,17 +620,17 @@ static void encWriteRegRetry (unsigned c
for (i = 0; i < c; i++) {
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x40 | regNo); /* write in regNo */
spi_write (data);
- enc_disable ();
- enc_enable ();
+ enc_disable (slave);
+ enc_enable (slave);
spi_write (0x1f); /* write reg 0x1f */
- enc_disable ();
+ enc_disable (slave);
spi_unlock (); /* we must unlock spi first */
@@ -649,14 +654,14 @@ static unsigned char encReadReg (unsigne
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x1f); /* read reg 0x1f */
bank = spi_read () & 0x3;
- enc_disable ();
- enc_enable ();
+ enc_disable (slave);
+ enc_enable (slave);
spi_write (regNo);
rxByte = spi_read ();
@@ -668,7 +673,7 @@ static unsigned char encReadReg (unsigne
rxByte = spi_read ();
}
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
return rxByte;
@@ -678,7 +683,7 @@ static void encReadBuff (unsigned short
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x20 | 0x1a); /* read buffer memory */
@@ -689,7 +694,7 @@ static void encReadBuff (unsigned short
spi_write (0);
}
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
}
@@ -697,7 +702,7 @@ static void encWriteBuff (unsigned short
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x60 | 0x1a); /* write buffer memory */
@@ -706,7 +711,7 @@ static void encWriteBuff (unsigned short
while (length--)
spi_write (*pBuff++);
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
}
@@ -714,12 +719,12 @@ static void encBitSet (unsigned char reg
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0x80 | regNo); /* bit field set */
spi_write (data);
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
}
@@ -727,12 +732,12 @@ static void encBitClr (unsigned char reg
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0xA0 | regNo); /* bit field clear */
spi_write (data);
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
}
@@ -740,11 +745,11 @@ static void encReset (void)
{
spi_lock ();
enc_cfg_spi ();
- enc_enable ();
+ enc_enable (slave);
spi_write (0xff); /* soft reset */
- enc_disable ();
+ enc_disable (slave);
spi_unlock ();
/* sleep 1 ms. See errata pt. 2 */
Index: u-boot-main/include/netdev.h
===================================================================
--- u-boot-main.orig/include/netdev.h
+++ u-boot-main/include/netdev.h
@@ -49,6 +49,8 @@ int davinci_emac_initialize(void);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
+int enc28j60_initialize(bd_t *bis, unsigned int spi_bus, unsigned int
spi_cs,
+ unsigned int max_hz, unsigned int mode);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
int fecmxc_initialize (bd_t *bis);
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