On 6.11.2017 09:34, Wilson Lee wrote: > From: Jeff Westfahl <jeff.westf...@ni.com> > > In legacy method, 1st stage bootloader was used to configure the HW > setting such as NAND timing. Hence, adding a config option in Zynq > NAND driver for the compatibility of device that using 1st stage > bootloder instead of U-boot SPL. > > This commit is to add config option > CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use > timing values set by the 1st stage bootloader, instead of the hard-coded > values in the Zynq NAND driver. > > Signed-off-by: Jeff Westfahl <jeff.westf...@ni.com> > Signed-off-by: Wilson Lee <wilson....@ni.com> > Cc: Joe Hershberger <joe.hershber...@ni.com> > Cc: Keng Soon Cheah <keng.soon.ch...@ni.com> > Cc: Chen Yee Chew <chen.yee.c...@ni.com> > Cc: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> > Cc: Michal Simek <michal.si...@xilinx.com> > Cc: Scott Wood <o...@buserror.net> > --- > drivers/mtd/nand/Kconfig | 7 +++++++ > drivers/mtd/nand/zynq_nand.c | 5 +++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 794410a..3f7edbb 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -164,6 +164,13 @@ config NAND_ZYNQ > This enables Nand driver support for Nand flash controller > found on Zynq SoC. > > +config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS > + bool "Enable use of 1st stage bootloader timing for NAND" > + depends on NAND_ZYNQ > + help > + This flag prevent U-boot reconfigure NAND flash controller and reuse > + the NAND timing from 1st stage bootloader. > + > comment "Generic NAND options" > > # Enhance depends when converting drivers to Kconfig which use this config > diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c > index 484f1bb..dec2c41 100644 > --- a/drivers/mtd/nand/zynq_nand.c > +++ b/drivers/mtd/nand/zynq_nand.c > @@ -35,6 +35,8 @@ > (0x1 << 4) | /* Clear interrupt */ \ > (0x1 << 6)) /* Disable ECC interrupt */ > > +#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS > + > /* Assuming 50MHz clock (20ns cycle time) and 3V operation */ > #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ > (0x2 << 17) | /* t_ar from nand_cycles */ \ > @@ -43,6 +45,7 @@ > (0x2 << 8) | /* t_rea from nand_cycles */ \ > (0x5 << 4) | /* t_wc from nand_cycles */ \ > (0x5 << 0)) /* t_rc from nand_cycles */ > +#endif > > > #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ > @@ -257,8 +260,10 @@ static int zynq_nand_init_nand_flash(int option) > > /* disable interrupts */ > writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); > +#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS > /* Initialize the NAND interface by setting cycles and operation mode */ > writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); > +#endif > if (option & NAND_BUSWIDTH_16) > writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor); > else >
Applied to my xilinx tree. Thanks, Michal _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
