On Dec 17, 2009, at 3:22 PM, Wolfgang Denk wrote:
> Dear Kumar Gala,
>
> In message <1260980960-15351-1-git-send-email-ga...@kernel.crashing.org> you
> wrote:
>> From: Becky Bruce <bec...@kernel.crashing.org>
>>
>> Signed-off-by: Becky Bruce <bec...@kernel.crashing.org>
>> Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
>> ---
>> include/asm-ppc/immap_85xx.h | 74
>> ++++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 74 insertions(+), 0 deletions(-)
>>
>> diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
>> index 43b3a2c..176a381 100644
>> --- a/include/asm-ppc/immap_85xx.h
>> +++ b/include/asm-ppc/immap_85xx.h
>> @@ -1562,6 +1562,77 @@ typedef struct par_io {
>> u8 res[8];
>> } par_io_t;
>>
>> +#ifdef CONFIG_SYS_FSL_CPC
>> +/*
>> + * Define a single offset that is the start of all the CPC register
>> + * blocks - if there is more than one CPC, we expect these to be
>> + * contiguous 4k regions
>> + */
>> +
>> +typedef struct cpc_corenet {
>> + u32 cpccsr0; /* Config/status reg */
>> +#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
>> +#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
>> +#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
>> +#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
>> +#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
>> +#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
>> + u32 res1;
>> + u32 cpccfg0; /* Configuration register */
>> +#define CPC_CFG0_SZ_MASK 0x00003fff
>> +#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
>> +#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
>> +#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
>> + u32 res2;
>> + u32 cpcewcr0; /* External Write reg 0 */
>> + u32 cpcewabr0; /* External write base reg 0 */
>> + u32 res3[2];
>> + u32 cpcewcr1; /* External Write reg 1 */
>> + u32 cpcewabr1; /* External write base reg 1 */
>> + u32 res4[54];
>> + u32 cpcsrcr1; /* SRAM control reg 1 */
>> +#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
>> +#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
>> + & CPC_SRCR1_SRBARU_MASK)
>> + u32 cpcsrcr0; /* SRAM control reg 0 */
>> +#define CPC_SRCR0_SRBARL_MASK 0xffff8000
>> +#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
>> +#define CPC_SRCR0_INTLVEN 0x00000100
>> +#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
>> +#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
>> +#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
>> +#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
>> +#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
>> +#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
>> +#define CPC_SRCR0_SRAMEN 0x00000001
>> + u32 res5[62];
>> + struct {
>> + u32 id; /* partition ID */
>> + u32 res;
>> + u32 alloc; /* partition allocation */
>> + u32 way; /* partition way */
>> + } partition_regs[16];
>> + u32 res6[704];
>> + u32 cpcerrinjhi; /* Error injection high */
>> + u32 cpcerrinjlo; /* Error injection lo */
>> + u32 cpcerrinjctl; /* Error injection control */
>> + u32 res7[5];
>> + u32 cpccaptdatahi; /* capture data high */
>> + u32 cpccaptdatalo; /* capture data low */
>> + u32 cpcaptecc; /* capture ECC */
>> + u32 res8[5];
>> + u32 cpcerrdet; /* error detect */
>> + u32 cpcerrdis; /* error disable */
>> +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit
>> disable */
>> + u32 cpcerrinten; /* errir interrupt enable */
>> + u32 cpcerrattr; /* error attribute */
>> + u32 cpcerreaddr; /* error extended address */
>> + u32 cpcerraddr; /* error address */
>> + u32 cpcerrctl; /* error control */
>> + u32 res9[105]; /* pad out to 4k */
>> +} cpc_corenet_t;
>> +#endif /* CONFIG_SYS_FSL_CPC */
>
> I really dislike mixing code (struct declaration) and macro defines.
> Please do not do this. I understand the intention, but the result is
> ugly and unreadable.
Whey you say macro's do you mean the mask #defines as well?
- k
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
