Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU
erratum A-007907") clears L1CSR2 for the boot core, but other cores
don't run through the workaround. Add similar code for secondary
cores to clear DCSTASHID field in L1CSR2 register.
Signed-off-by: York Sun <york....@nxp.com>
---
arch/powerpc/cpu/mpc85xx/release.S | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index 0e0daf5..e1f1208 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -184,12 +184,18 @@ __secondary_start_page:
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+ mfspr r8, L1CSR2
+ clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
+ mtspr L1CSR2, r8
+#else
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
--
2.7.4
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