From: Dave Liu <dave...@freescale.com>

In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu <dave...@freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3be7e22..adc4f6e 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t 
*popts,
                        /* Don't set up boundaries for other CS
                         * other than CS0, if bank interleaving
                         * is enabled and not CS2+CS3 interleaved.
+                        * But we need to set the ODT_RD_CFG and
+                        * ODT_WR_CFG for CS1_CONFIG here.
                         */
+                       set_csn_config(i, ddr, popts, dimm_params);
                        break;
                }
 
-- 
1.6.0.6

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