On 12.9.2017 20:05, Tom McLeod wrote: > Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board > contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports > booting from SD. > > Signed-off-by: Tom McLeod <tom.mcl...@opalkelly.com> > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/zynq-syzygy-hub.dts | 72 ++ > board/opalkelly/zynq/MAINTAINERS | 6 + > board/opalkelly/zynq/Makefile | 9 + > board/opalkelly/zynq/board.c | 1 + > .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 1078 > ++++++++++++++++++++ > .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 103 ++
Can you please look at board/topic/zynq/* and try to minimalize these
ps7_init* files?
At least remove functions related to silicon v1/v2?
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ } else {
> configs/syzygy_hub_defconfig | 57 ++
> include/configs/syzygy_hub.h | 72 ++
> 9 files changed, 1399 insertions(+)
> create mode 100644 arch/arm/dts/zynq-syzygy-hub.dts
> create mode 100644 board/opalkelly/zynq/MAINTAINERS
> create mode 100644 board/opalkelly/zynq/Makefile
> create mode 100644 board/opalkelly/zynq/board.c
> create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
> create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
> create mode 100644 configs/syzygy_hub_defconfig
> create mode 100644 include/configs/syzygy_hub.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1d6cee2..c15d94f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
> zynq-zc706.dtb \
> zynq-zed.dtb \
> zynq-zybo.dtb \
> + zynq-syzygy-hub.dtb \
as I see we should sort it :-)
> zynq-microzed.dtb \
> zynq-picozed.dtb \
> zynq-topic-miami.dtb \
> diff --git a/arch/arm/dts/zynq-syzygy-hub.dts
> b/arch/arm/dts/zynq-syzygy-hub.dts
> new file mode 100644
> index 0000000..c98ef01
> --- /dev/null
> +++ b/arch/arm/dts/zynq-syzygy-hub.dts
> @@ -0,0 +1,72 @@
> +/*
> + * SYZYGY Hub DTS
> + *
> + * Copyright (C) 2011 - 2015 Xilinx
> + * Copyright (C) 2017 Opal Kelly Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "SYZYGY Hub";
> + compatible = "xlnx,zynq-7000";
compatible string should contain also information about your board.
It means you should record your prefix in Linux kernel first and then
use it here.
compatible = "opalkelly,syzygy-hub-vXX", "opalkelly,syzygy-hub",
"xlnx,zynq-7000";
The rest is good.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs
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