Hi Tuomas,
On Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen
<tuomas.tynkky...@iki.fi> wrote:
> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
> The 'highmem=off' part is required for things to work as the PCI code
> in U-Boot doesn't seem to support 64-bit BARs.
>
> Signed-off-by: Tuomas Tynkkynen <tuomas.tynkky...@iki.fi>
> ---
> v2:
> - no 'default n'
> - remove unnecessary non-DM struct field (inherited from the Xilinx driver)
> - fix doc comment problems (inherited from the Xilinx driver)
> - use the new generic memory mapped config space helpers
> ---
> drivers/pci/Kconfig | 8 +++
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_ecam_generic.c | 143
> ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 152 insertions(+)
> create mode 100644 drivers/pci/pcie_ecam_generic.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index e2a1c0a409..648dff7543 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -33,6 +33,14 @@ config PCI_PNP
> help
> Enable PCI memory and I/O space resource allocation and assignment.
>
> +config PCIE_ECAM_GENERIC
> + bool "Generic ECAM-based PCI host controller support"
> + default n
Still 'default n' here?
> + depends on DM_PCI
> + help
> + Say Y here if you want to enable support for generic ECAM-based
> + PCIe host controllers, such as the one emulated by QEMU.
> +
> config PCIE_DW_MVEBU
> bool "Enable Armada-8K PCIe driver (DesignWare core)"
> default n
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index ad44e83996..5eb12efbf5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
> endif
> obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
>
> +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
> obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
> obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
> obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
> diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
> new file mode 100644
> index 0000000000..2758f90de1
> --- /dev/null
> +++ b/drivers/pci/pcie_ecam_generic.c
> @@ -0,0 +1,143 @@
> +/*
> + * Generic PCIE host provided by e.g. QEMU
> + *
> + * Heavily based on drivers/pci/pcie_xilinx.c
> + *
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <pci.h>
> +
> +#include <asm/io.h>
> +
> +/**
> + * struct generic_ecam_pcie - generic_ecam PCIe controller state
> + * @cfg_base: The base address of memory mapped configuration space
> + */
> +struct generic_ecam_pcie {
> + void *cfg_base;
> +};
> +
> +/**
> + * pci_generic_ecam_conf_address() - Calculate the address of a config access
nits: please add one blank line here
> + * @bus: Pointer to the PCI bus
> + * @bdf: Identifies the PCIe device to access
> + * @offset: The offset into the device's configuration space
> + * @paddress: Pointer to the pointer to write the calculates address to
> + *
> + * Calculates the address that should be accessed to perform a PCIe
> + * configuration space access for a given device identified by the PCIe
> + * controller device @pcie and the bus, device & function numbers in @bdf. If
> + * access to the device is not valid then the function will return an error
> + * code. Otherwise the address to access will be written to the pointer
> pointed
> + * to by @paddress.
> + */
> +static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf,
> + uint offset, void **paddress)
> +{
> + struct generic_ecam_pcie *pcie = dev_get_priv(bus);
> + void *addr;
> +
> + addr = pcie->cfg_base;
> + addr += PCI_BUS(bdf) << 20;
> + addr += PCI_DEV(bdf) << 15;
> + addr += PCI_FUNC(bdf) << 12;
> + addr += offset;
> + *paddress = addr;
> +
> + return 0;
> +}
> +
> +/**
> + * pci_generic_ecam_read_config() - Read from configuration space
nits: please add one blank line here
> + * @bus: Pointer to the PCI bus
> + * @bdf: Identifies the PCIe device to access
> + * @offset: The offset into the device's configuration space
> + * @valuep: A pointer at which to store the read value
> + * @size: Indicates the size of access to perform
> + *
> + * Read a value of size @size from offset @offset within the configuration
> + * space of the device identified by the bus, device & function numbers in
> @bdf
> + * on the PCI bus @bus.
> + */
> +static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,
> + uint offset, ulong *valuep,
> + enum pci_size_t size)
> +{
> + return pci_generic_mmap_read_config(bus,
> pci_generic_ecam_conf_address,
> + bdf, offset, valuep, size);
> +}
> +
> +/**
> + * pci_generic_ecam_write_config() - Write to configuration space
nits: please add one blank line here
> + * @bus: Pointer to the PCI bus
> + * @bdf: Identifies the PCIe device to access
> + * @offset: The offset into the device's configuration space
> + * @value: The value to write
> + * @size: Indicates the size of access to perform
> + *
> + * Write the value @value of size @size from offset @offset within the
> + * configuration space of the device identified by the bus, device & function
> + * numbers in @bdf on the PCI bus @bus.
> + */
> +static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
> + uint offset, ulong value,
> + enum pci_size_t size)
> +{
> + return pci_generic_mmap_write_config(bus,
> pci_generic_ecam_conf_address,
> + bdf, offset, value, size);
> +}
> +
> +/**
> + * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
nits: please add one blank line here
> + * @dev: A pointer to the device being operated on
> + *
> + * Translate relevant data from the device tree pertaining to device @dev
> into
> + * state that the driver will later make use of. This state is stored in the
> + * device's private data structure.
> + *
> + * Return: 0 on success, else -EINVAL
> + */
> +static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct generic_ecam_pcie *pcie = dev_get_priv(dev);
> + struct fdt_resource reg_res;
> + DECLARE_GLOBAL_DATA_PTR;
> + int err;
> +
> + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
> + 0, ®_res);
> + if (err < 0) {
> + error("\"reg\" resource not found\n");
> + return err;
> + }
> +
> + pcie->cfg_base = map_physmem(reg_res.start,
> + fdt_resource_size(®_res),
> + MAP_NOCACHE);
> +
> + return 0;
> +}
> +
> +static const struct dm_pci_ops pci_generic_ecam_ops = {
> + .read_config = pci_generic_ecam_read_config,
> + .write_config = pci_generic_ecam_write_config,
> +};
> +
> +static const struct udevice_id pci_generic_ecam_ids[] = {
> + { .compatible = "pci-host-ecam-generic" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pci_generic_ecam) = {
> + .name = "pci_generic_ecam",
> + .id = UCLASS_PCI,
> + .of_match = pci_generic_ecam_ids,
> + .ops = &pci_generic_ecam_ops,
> + .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
> + .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
> +};
> --
Other than above nits:
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Regards,
Bin
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