On Mon, 2017-08-28 at 17:14 +0000, York Sun wrote: > +Xiaowei > > On 08/28/2017 10:09 AM, Joakim Tjernlund wrote: > > On Mon, 2017-08-28 at 16:55 +0000, York Sun wrote: > > > On 08/28/2017 09:48 AM, Joakim Tjernlund wrote: > > > > FSL PCIe controller drivers before REV 3 has this test for link up: > > > > enabled = ltssm >= PCI_LTSSM_L0; > > > > > > > > We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) when > > > > non ready > > > > for PCI transaktions. When FSL PCIe controller tries to access this > > > > device, it > > > > hangs forever. > > > > > > > > Is LTSSM=0x51 really a "legal" state for link up? > > > > If not, what is a suitable range(maybe LO <= ltssm <= L0s(0x27)) ? > > > > > > > > Jocke > > > > > > > > BTW, the same test is valid in Linux too. > > > > > > > > > > Jocke, > > > > > > I am not an expert on PCIe. Please if this thread is helpful, > > > > Me neither .. :) > > > > > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F801519%2F&data=01%7C01%7Cyork.sun%40nxp.com%7Cf46ff5111ba04e631a9b08d4ee377ecc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=n9%2B2NIjEvsMBCljRLHS6NVVN4ANa3nBGpwUjI4Od%2Bhs%3D&reserved=0. > > > > It mentions polling compliance but this driver already tests for: > > if (ltssm < LTSSM_PCIE_L0) > > return 0; > > return 1; > > > > It just adds some delay if the device is in Polling Compliance to see if > > that > > changes to L0. > > Since both layerscape and fsl >= rev 3 already require ltssm to be == L0, I > > suspect > > the ltssm >= L0 is bogus. > > > > Xiaowei, can you comment? > > York
Ping? Should I just send a patch ? Jocke _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
