On 08/30/2017 10:36 AM, Chee, Tien Fong wrote:
> On Sel, 2017-08-29 at 13:59 +0200, Marek Vasut wrote:
>> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.c...@intel.com>
>>>
>>> Add function for both multiple DRAM bank and single DRAM bank size
>>> initialization. This common functionality could be used by every
>>> single
>>> SOCFPGA board.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
>>> ---
>>> arch/arm/mach-socfpga/board.c | 12 ++++++++++++
>>> include/configs/socfpga_common.h | 1 +
>>> 2 files changed, 13 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
>>> socfpga/board.c
>>> index a41d089..3f2e30a 100644
>>> --- a/arch/arm/mach-socfpga/board.c
>>> +++ b/arch/arm/mach-socfpga/board.c
>>> @@ -29,6 +29,18 @@ int board_init(void)
>>> return 0;
>>> }
>>>
>>> +int dram_init_banksize(void)
>>> +{
>>> +#if !defined(CONFIG_SYS_SDRAM_BASE) &&
>>> !defined(CONFIG_SYS_SDRAM_SIZE)
>>> + fdtdec_setup_memory_banksize();
>> This should work on al boards, so why do you need this macro ?
>> Also, this should go into arch/arm/ , not board/
>>
> In case these macros are not defined, then we need to get the info from
> DTS. This is in arch/arm/mach-socpfga/board.c . I found some in
> arch/arm, and other in board/ .
Every socfpga platform in u-boot has a dts, so you can always extract
the memory config from it and it's the preferred method.
>>>
>>> +#else
>>> + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>>> + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
>>> +#endif
>>> +
>>> + return 0;
>>> +}
>>> +
>>> #ifdef CONFIG_USB_GADGET
>>> struct dwc2_plat_otg_data socfpga_otg_data = {
>>> .usb_gusbcfg = 0x1417,
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index c15d244..05b03bd 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -47,6 +47,7 @@
>>> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>>>
>>> #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
>>> +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
>>> #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>>> #define CONFIG_SYS_TEXT_BASE 0x08000040
>>> #else
>>>
--
Best regards,
Marek Vasut
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