Dear Seunghyyeon Rhee, 2009/12/3 Seunghyeon Rhee <[email protected]>: > Minkyu Kang worte: >> Dear Seunghyeon Rhee, >> >> 2009/11/28 "Seunghyeon Rhee" <[email protected]>: >> >>> The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control >>> for S3C6400. In the configuration of SMDK6400, however, two 16-bit >>> mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit >>> memory bus and there is no need to contorl CKE for each chip >>> separately. AFAIK, CKE1 is not at all connected. Only CKE0 is >>> used. Futhermore, it should be '0' always for S3C6410. When tested >>> with a board which has a S3C6410 and the same memory configuration, >>> a side effect is obsearved that u-boot command "reset" doesn't work >>> leading to system hang. Leaving the bit clear is safe in most cases. >>> >>> Signed-off-by: Seunghyeon Rhee <[email protected]> >>> --- >>> include/s3c6400.h | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) >>> >>> diff --git a/include/s3c6400.h b/include/s3c6400.h >>> index e527c08..7229ea6 100644 >>> --- a/include/s3c6400.h >>> +++ b/include/s3c6400.h >>> @@ -817,7 +817,7 @@ >>> /*----------------------------------------------------------------------- >>> * Physical Memory Map >>> */ >>> -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ >>> +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ >>> #define DMC1_MEM_CFG2 0xB45 >>> #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) >>> */ >>> #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ >>> -- >>> 1.6.2.5 >>> >>> >>> -- >>> Seunghyeon Rhee, Ph.D. / Director >>> LPM Technology Inc. >>> T +82-70-8255-6007 F +82-2-6442-6462 >>> M +82-10-2790-0657 >>> >>> >> >> Please rebase this patch. >> s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h >> >> Thanks >> Minkyu Kang >> > > The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control > for S3C6400. In the configuration of SMDK6400, however, two 16-bit > mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit > memory bus and there is no need to control CKE for each chip > separately. AFAIK, CKE1 is not at all connected. Only CKE0 is > used. Futhermore, it should be '0' always for S3C6410. When tested > with a board which has a S3C6410 and the same memory configuration, > a side effect is observed that u-boot command "reset" doesn't work > leading to system hang. Leaving the bit clear is safe in most cases. > > Signed-off-by: Seunghyeon Rhee <[email protected]> > --- > include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h > b/include/asm-arm/arch-s3c64xx/s3c6400.h > index e527c08..10b3324 100644 > --- a/include/asm-arm/arch-s3c64xx/s3c6400.h > +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h > @@ -817,9 +817,9 @@ > /*----------------------------------------------------------------------- > * Physical Memory Map > */ > -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ > +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ > #define DMC1_MEM_CFG2 0xB45 > -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ > +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) > */ > #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ > > /* Memory Parameters */ > -- > 1.6.2.5 > > > Seunghyeon Rhee, Ph.D. / Director > LPM Technology Inc. > T +82-70-8255-6007 F +82-2-6442-6462 > M +82-10-2790-0657 >
applied to u-boot-samsung Thanks Minkyu Kang -- from. prom. www.promsoft.net _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
