+}
+
+static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand)
+{
+ int timeout = NANDC_V6_DEF_TIMEOUT;
+ int reg;
+
+ while (timeout--) {
+ reg = readl(rknand->regs + NANDC_REG_V6_FLCTL);
+
+ if ((reg & NANDC_V6_FL_XFER_READY) != 0)
+ break;
+
+ udelay(1);
+ }
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
+static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
+ int len = mtd->oobsize - offset;
+
+ if (len <= 0)
+ return;
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1);
+
+ rockchip_nand_read_buf(mtd, oob + offset, len);
+}
+
+static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8
*oob)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
+ int len = mtd->oobsize - offset;
+
+ if (len <= 0)
+ return;
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1);
+
+ rockchip_nand_write_buf(mtd, oob + offset, len);
+}
+
+
+static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info
*mtd,
+ struct nand_chip *chip,
+ uint8_t *buf,
+ int oob_required,
+ int page)
+{
+ struct rk_nand *rknand = to_rknand(chip->controller);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0;
+ unsigned int max_bitflips = 0;
+ int ret, step, bch_st;
+ int offset = page * mtd->writesize;
+
+ if (rknand->bootromblocks && (offset < (7 * mtd->erasesize)))
+ rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC);
+
+ rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, 0);
+
+ for (step = 0; step < ecc->steps; step++) {
+ int data_off = step * ecc->size;
+ int oob_off = step * (ecc->bytes + ecc->prepad);
+ u8 *data = buf + data_off;
+ u8 *oob = chip->oob_poi + oob_off;
+
+ ret = rockchip_nand_wait_pio_xfer_done(rknand);
+ if (ret)
+ return ret;
+
+ bch_st = readl(rknand->regs + NANDC_REG_V6_BCHST);
+
+ if (bch_st & NANDC_V6_BCH0_ST_ERR) {
+ mtd->ecc_stats.failed++;
+ max_bitflips = -1;
+ } else {
+ ret = NANDC_V6_ECC_ERR_CNT0(bch_st);
+ mtd->ecc_stats.corrected += ret;
+ max_bitflips = max_t(unsigned int, max_bitflips, ret);
+ }
+
+ if ((step + 1) < ecc->steps)
+ rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ,
+ (step + 1) & 0x1);
+
+ memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE *
+ (step & 1), ecc->size);
+
+ if (step & 1)
+ memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE1, 4);
+ else
+ memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE0, 4);
+ }
+
+ rockchip_nand_read_extra_oob(mtd, chip->oob_poi);
+
+ if (rknand->bootromblocks)
+ rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
+
+ return max_bitflips;
+}
+
+static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd,
+ int page,
+ const u8 *oob,
+ bool bootromblocks)
+{
+ int pages_per_block = mtd->erasesize / mtd->writesize;
+ int offset = page * mtd->writesize;
+
+ if ((offset < (2 * mtd->erasesize)) || !(page % 2) ||
+ (offset >= (7 * mtd->erasesize)) || !bootromblocks)
+ return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] <<
24);
+
+ return (page % pages_per_block + 1) * 4;
+}
+
+static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info
*mtd,
+ struct nand_chip *chip,
+ const uint8_t *buf,
+ int oob_required,
+ int page)
+{
+ struct rk_nand *rknand = to_rknand(chip->controller);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0;
+ int ret, index, step = 0;
+ int offset = page * mtd->writesize;
+ int data_off = step * ecc->size;
+ int oob_off = step * (ecc->bytes + ecc->prepad);
+ const u8 *data = buf + data_off;
+ const u8 *oob = chip->oob_poi + oob_off;
+
+ if (rknand->bootromblocks && (offset < (7 * mtd->erasesize)))
+ rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC);
+
+ index = rockchip_nand_make_bootrom_compat(mtd, page, oob,
+ rknand->bootromblocks);
+
+ memcpy_toio(sram_base, data, ecc->size);
+ memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, &index,
ecc->prepad);
+
+ for (step = 1; step <= ecc->steps; step++) {
+ rockchip_nand_pio_xfer_start(rknand, NANDC_V6_WRITE,
+ (step - 1) & 0x1);
+
+ data_off = step * ecc->size;
+ oob_off = step * (ecc->bytes + ecc->prepad);
+ data = buf + data_off;
+ oob = chip->oob_poi + oob_off;
+
+ if (step < ecc->steps) {
+ memcpy_toio(sram_base + NANDC_REG_V6_SRAM_SIZE *
+ (step & 1), data, ecc->size);
+ if (step & 1)
+ memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE1,
+ oob, ecc->prepad);
+ else
+ memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0,
+ oob, ecc->prepad);
+ }
+
+ ret = rockchip_nand_wait_pio_xfer_done(rknand);
+ if (ret)
+ return ret;
+ }
+
+ rockchip_nand_write_extra_oob(mtd, chip->oob_poi);
+
+ rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
+
+ return 0;
+}
+
+static const u8 strengths[] = {60, 40, 24, 16};
+
+static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd,
+ struct nand_ecc_ctrl *ecc)
+{
+ uint32_t max_strength, index;
+
+ max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 /
14;
+
+ for (index = 0; index < ARRAY_SIZE(strengths); index++)
+ if (max_strength >= strengths[index])
+ break;
+
+ if (index >= ARRAY_SIZE(strengths))
+ return -ENOTSUPP;
+
+ return strengths[index];
+}
+
+static bool rockchip_nand_strength_is_valid(int strength)
+{
+ uint32_t index;
+
+ for (index = 0; index < ARRAY_SIZE(strengths); index++)
+ if (strength == strengths[index])
+ break;
+
+ if (index == ARRAY_SIZE(strengths))
+ return false;
+
+ return true;
+}
+
+static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
+ struct nand_ecc_ctrl *ecc)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct rk_nand *rknand = to_rknand(chip->controller);
+ uint32_t strength;
+ int index;
+
+ ecc->prepad = 4;
+ ecc->steps = mtd->writesize / ecc->size;
+
+ if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node,
+ "rockchip,protect-bootrom-blocks"))
+ rknand->bootromblocks = true;
+ else
+ rknand->bootromblocks = false;
+
+ if (rockchip_nand_strength_is_valid(ecc->strength))
+ strength = ecc->strength;
+ else
+ strength = rockchip_nand_ecc_max_strength(mtd, ecc);
+
+ rockchip_nand_hw_ecc_setup(mtd, ecc, strength);
+
+ rknand->ecc_strength = ecc->strength;
+
+ nand_oob_fix.eccbytes = ecc->bytes * ecc->steps;
+ for (index = 0; index < ecc->bytes; index++)
+ nand_oob_fix.eccpos[index] = index + ecc->prepad;
+ ecc->layout = &nand_oob_fix;
+
+ if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rockchip_nand_ecc_init(struct mtd_info *mtd,
+ struct nand_ecc_ctrl *ecc)
+{
+ int ret;
+
+ switch (ecc->mode) {
+ case NAND_ECC_HW_SYNDROME:
+ ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc);
+ if (ret)
+ return ret;
+ ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page;
+ ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page;
+ break;
+ case NAND_ECC_SOFT_BCH:
+ case NAND_ECC_NONE:
+ case NAND_ECC_SOFT:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rockchip_nand_chip_init(int node, struct rk_nand *rknand,
int devnum)
+{
+ const void *blob = gd->fdt_blob;
+ struct nand_chip *chip;
+ struct mtd_info *mtd;
+ int ret;
+
+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+
+ chip->chip_delay = 50;
+ chip->flash_node = node;
+ chip->select_chip = rockchip_nand_select_chip;
+ chip->cmd_ctrl = rockchip_nand_cmd_ctrl;
+ chip->read_buf = rockchip_nand_read_buf;
+ chip->write_buf = rockchip_nand_write_buf;
+ chip->read_byte = rockchip_nand_read_byte;
+ chip->dev_ready = rockchip_nand_dev_ready;
+ chip->controller = &rknand->controller;
+
+ rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1);
+
+ if (rknand->banks[devnum] < 0)
+ return -EINVAL;
+
+ mtd = nand_to_mtd(chip);
+ mtd->name = "rknand";
+
+ ret = nand_scan_ident(mtd, 1, NULL);
+ if (ret)
+ return ret;
+
+ ret = rockchip_nand_ecc_init(mtd, &chip->ecc);
+ if (ret) {
+ debug("rockchip_nand_ecc_init failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = nand_scan_tail(mtd);
+ if (ret) {
+ debug("nand_scan_tail failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = nand_register(devnum, mtd);
+ if (ret) {
+ debug("Failed to register mtd device: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_nand_chips_init(int node, struct rk_nand *rknand)
+{
+ const void *blob = gd->fdt_blob;
+ int nand_node;
+ int ret, i = 0;
+
+ for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+ nand_node = fdt_next_subnode(blob, nand_node)) {
+ ret = rockchip_nand_chip_init(nand_node, rknand, i++);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_nand_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct rk_nand *rknand;
+ fdt_addr_t regs;
+ int node;
+ int ret;
+
+ rknand = kzalloc(sizeof(*rknand), GFP_KERNEL);
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
+
+ if (node < 0) {
+ debug("Nand node not found\n");
+ goto err;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ debug("Nand disabled in device tree\n");
+ goto err;
+ }
+
+ regs = fdtdec_get_addr(blob, node, "reg");
+ if (regs == FDT_ADDR_T_NONE) {
+ debug("Nand address not found\n");
+ goto err;
+ }
+
+ rknand->regs = (void *)regs;
+
+ spin_lock_init(&rknand->controller.lock);
+ init_waitqueue_head(&rknand->controller.wq);
+
+ rockchip_nand_init(rknand);
+
+ ret = rockchip_nand_chips_init(node, rknand);
+ if (ret) {
+ debug("Failed to init nand chips\n");
+ goto err;
+ }
+
+ return;
+err:
+ kfree(rknand);
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ struct mtd_info *mtd;
+
+ mtd = get_nand_dev_by_index(0);
+ return nand_read_skip_bad(mtd, offs, &size, NULL, size, (u_char
*)dst);
+}
+
+void nand_deselect(void) {}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4a0947c..0e68788 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -157,6 +157,7 @@ enum fdt_compat_id {
COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0
bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1
bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2
bridge */
+ COMPAT_ROCKCHIP_NANDC, /* Rockchip NAND controller */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 107a892..4a8a8d7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -70,6 +70,7 @@ static const char * const
compat_names[COMPAT_COUNT] = {
COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+ COMPAT(ROCKCHIP_NANDC, "rockchip,nandc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
