On 08/18/2017 10:16 AM, Marek Vasut wrote: > On 08/17/2017 09:31 AM, Ran Wang wrote: >> USB High Speed (HS) EYE Height Adjustment >> USB HS speed eye diagram fails with the default value at >> many corners, particularly at a high temperature >> >> Optimal eye at TXREFTUNE value to 1001 is observed, change >> set the same value. >> >> Signed-off-by: Ran Wang <ran.wan...@nxp.com> >> --- >> Change in v3: >> Use inline function to make code cleaner. >> >> Change in v2: >> In function erratum_a009008(): >> 1.Put a blank line after variable declaration. >> 2.Move common code together. >> >> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++ >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 >> ++++++++++++++++++++++ >> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ >> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + >> 4 files changed, 39 insertions(+) >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >> index 5825f9b..300f5ce 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >> @@ -22,6 +22,7 @@ config ARCH_LS1043A >> select SYS_FSL_ERRATUM_A009942 >> select SYS_FSL_ERRATUM_A010315 >> select SYS_FSL_ERRATUM_A010539 >> + select SYS_FSL_ERRATUM_A009008 >> select SYS_FSL_HAS_DDR3 >> select SYS_FSL_HAS_DDR4 >> select ARCH_EARLY_INIT_R >> @@ -43,6 +44,7 @@ config ARCH_LS1046A >> select SYS_FSL_ERRATUM_A009942 >> select SYS_FSL_ERRATUM_A010165 >> select SYS_FSL_ERRATUM_A010539 >> + select SYS_FSL_ERRATUM_A009008 >> select SYS_FSL_HAS_DDR4 >> select SYS_FSL_SRDS_2 >> select ARCH_EARLY_INIT_R >> @@ -79,6 +81,7 @@ config ARCH_LS2080A >> select SYS_FSL_ERRATUM_A009942 >> select SYS_FSL_ERRATUM_A010165 >> select SYS_FSL_ERRATUM_A009203 >> + select SYS_FSL_ERRATUM_A009008 >> select ARCH_EARLY_INIT_R >> select BOARD_EARLY_INIT_F >> >> @@ -222,6 +225,10 @@ config SYS_FSL_ERRATUM_A010315 >> config SYS_FSL_ERRATUM_A010539 >> bool "Workaround for PIN MUX erratum A010539" >> >> +config SYS_FSL_ERRATUM_A009008 >> + bool "Workaround for USB PHY erratum A009008" >> + >> + >> config MAX_CPUS >> int "Maximum number of CPUs permitted for Layerscape" >> default 4 if ARCH_LS1043A >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> index aee1ffa..7e5288b 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> @@ -52,6 +52,29 @@ bool soc_has_aiop(void) >> return false; >> } >> >> +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) > > Drop the inline.
Marek, please explain why we should drop the "inline"? I suggested the "inline" based on v2 patch. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
