On 07/24/2017 11:34 PM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and > moves existing register space definaton of CCI-400 bus > from immap_lsch2 to fsl_immap, so that it can be used > for both chasis 2 and chasis 3. > > "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET > is introduced in Kconfig > > Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com> > --- > v3: > This is v3 for > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F731464%2F&data=01%7C01%7Cyork.sun%40nxp.com%7Cc9bc50608f604210cb7908d4d3272bec%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=czDJiEhPXl%2ByYW%2BNKyodw5hOrywjRvw39JoVccPYE0Y%3D&reserved=0 > v4: > Header file included in middle of the file in cpu.c > > README | 9 ++++ > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 ++++++ > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 +++-- > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 49 > --------------------- > board/freescale/ls1012afrdm/ls1012afrdm.c | 4 +- > board/freescale/ls1012aqds/ls1012aqds.c | 4 +- > board/freescale/ls1012ardb/ls1012ardb.c | 3 +- > board/freescale/ls1021aqds/ls1021aqds.c | 9 ++-- > include/fsl_immap.h | 51 > ++++++++++++++++++++++ > 10 files changed, 94 insertions(+), 59 deletions(-) >
Ashish, This patch shouldn't include LS1021AQDS. It has ARMv7 core. It should be moved to your 2nd patch. You are breaking all LS1021A board with this patch. Please fix. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
