Only cosmetic issues found in this set. Please check more comments on
patch 4.
On 07/09/2017 07:41 PM, Ran Wang wrote:
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXREFTUNE value to 1001 is observed, change
> set the same value.
>
> Signed-off-by: Ran Wang <ran.wan...@nxp.com>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25
> ++++++++++++++++++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
> 4 files changed, 39 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index d8b285d..eebfcfe 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -22,6 +22,7 @@ config ARCH_LS1043A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010315
> select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_HAS_DDR3
> select SYS_FSL_HAS_DDR4
> select ARCH_EARLY_INIT_R
> @@ -42,6 +43,7 @@ config ARCH_LS1046A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010165
> select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_HAS_DDR4
> select SYS_FSL_SRDS_2
> select ARCH_EARLY_INIT_R
> @@ -77,6 +79,7 @@ config ARCH_LS2080A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010165
> select SYS_FSL_ERRATUM_A009203
> + select SYS_FSL_ERRATUM_A009008
> select ARCH_EARLY_INIT_R
> select BOARD_EARLY_INIT_F
>
> @@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315
> config SYS_FSL_ERRATUM_A010539
> bool "Workaround for PIN MUX erratum A010539"
>
> +config SYS_FSL_ERRATUM_A009008
> + bool "Workaround for USB PHY erratum A009008"
> +
> +
> config MAX_CPUS
> int "Maximum number of CPUs permitted for Layerscape"
> default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 0943e83..a91f85e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,29 @@ bool soc_has_aiop(void)
> return false;
> }
>
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
Put a blank line after variable declaration.
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
> +#elif defined(CONFIG_ARCH_LS2080A)
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
Move the common code together.
Same comment goes to other patches in this set.
York
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