On Mon, Nov 16, 2009 at 05:49:55PM +0000, Nick Thompson wrote:
> static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
> {
> - int dummy;
> + u_int32_t val;
>
> - dummy = emif_regs->NANDF1ECC;
> + val = readl(&emif_regs->NANDF1ECC);
"val =" can be omitted, which would keep it clear that it is a dummy read.
> - /* FIXME: only chipselect 0 is supported for now */
> - emif_regs->NANDFCR |= 1 << 8;
> + val = readl(&emif_regs->NANDFCR);
> + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
> + writel(val, &emif_regs->NANDFCR);
Do you need to clear the bit corresponding to the previous chipselect?
Otherwise, ACK.
-Scott
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