From: Paul Burton <paul.bur...@imgtec.com>
Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.
Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
---
Changes in v2:
- set default value for Boston in arch/mips/Kconfig
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77d1ac65d2..07488fe651 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -224,6 +224,7 @@ config ROM_EXCEPTION_VECTORS
config MIPS_CM_BASE
hex "MIPS CM GCR Base Address"
depends on MIPS_CM
+ default 0x16100000 if TARGET_BOSTON
default 0x1fbf8000
help
The physical base address at which to map the MIPS Coherence Manager
--
2.11.0
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