This series adds SPI support for the RK3399 (SPI1 and SPI5). This
consists of the following individual changes:
- clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2,
SPI 4 and SPI5)
- pinctrl for SPI1 and SPI5
- changes the SPI module input clock to 198MHz (instead of 99MHz) for
the RK3399 to improve the available bitrates at higher frequencies
(e.g. adding the 39MBit and 28MBit operating points)
- modifies the calculation of the top frequency permissible (as the
49.5MBit operating point had not been permissible due to a hard
limit at 48MBit)
In addition to these changes, the divider calculation for the baudrate
is changed to
- try hard not to exceed the requested rate (i.e. err towards a
lower rate)
- not to overflow the divider field (which may result in a very large
actual baudrate for very small requested baudrates)
To make it easier to track this change set (and avoid me sending patch
series with broken cover letters), this now also includes the change
to have a per-board SPI config:
rockchip: spl: rk3399: prepare to have SPI config per-board
To support SPI flashes (via the device model) and enable loading of
later-stage images from SPI in SPL, we need a few adjustments to the
common configuration header for the RK3399:
- enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common)
- move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3399_common) to defconfig
Changes in v4:
- rewrite to not introduce a chip-specific define, add a dynamic
module input rate selection and unify the bitrate handling for hard
and soft limits.
(replaces 2 earlier commits mentioned in the commit message)
- added an more defensive calculation of the baudrate divider after
receiving complaints from the board-verification team
- changed rk3399_common.h to allow a per-board SPI config through
defconfig (previously a stand-along patch, but it slipped into
the series at some point and messed up the coverletter of some
of the submissions)
Changes in v3:
- replaced macro-pasting with a lookup table to improve readability
(as suggested by Simon)
Changes in v2:
- fixes a wrong macro usage, which caused the SPI module input clock
frequency to be significantly higher than intended
- frequencies have now been validated using an oscilloscope (keep in mind
that all frequencies are derived from a 99MHz module input clock) at the
following measurement points (assuming the other fix for the usage of
DIV_RATE from the series):
* 1 MHz ... 0.99 MHz
* 5 MHz ... 4.95 MHz
* 10 MHz ... 9.9 MHz
* 30 MHz ... 33 MHz
* 50 MHz ... 49.5 MHz
- fixes an off-by-one for the RK3399 that cause the SPI module input
clock to be misstated as 84MHz (even though it was running at 99MHz)
Jakob Unterwurzacher (1):
rockchip: spi: enable support for the rk_spi driver for the RK3399
Philipp Tomsich (6):
rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
rockchip: clk: rk3399: fix off-by one during rate calculation in
i2c/spi_set_rate
rockchip: spi: rk_spi: dynamically select an module input rate
rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate
setting
rockchip: pinctrl: rk3399: add support for the SPI5 controller
rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for
SPL
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 +++
arch/arm/include/asm/arch-rockchip/periph.h | 3 +
drivers/clk/rockchip/clk_rk3399.c | 113 ++++++++++++++++++++++--
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 ++++
drivers/spi/rk_spi.c | 62 ++++++++++---
drivers/spi/rk_spi.h | 9 +-
include/configs/rk3399_common.h | 3 +
7 files changed, 201 insertions(+), 18 deletions(-)
--
1.9.1
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