The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.
Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
---
cpu/mpc8xxx/pci_cfg.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
index 9c7d92c..ea129c5 100644
--- a/cpu/mpc8xxx/pci_cfg.c
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -210,10 +210,12 @@ static struct pci_info pci_config_info[] =
.cfg = (1 << 2) | (1 << 4),
},
};
+#elif defined(CONFIG_FSL_CORENET)
#else
#error Need to define pci_config_info for processor
#endif
+#ifndef CONFIG_FSL_CORENET
int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent)
{
return ((1 << host_agent) & pci_config_info[trgt].agent);
@@ -223,3 +225,4 @@ int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
{
return ((1 << io_sel) & pci_config_info[trgt].cfg);
}
+#endif
--
1.6.0.6
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