This patch adds a new ARM AT91RM9200 board, named EB+CPUx9K2.
* support for EB+CPUx9K2 board by BuS Elektronik GmbH & Co. KG
* select via make eb_cpux9k2_config
Signed-off-by: Jens Scharsig <e...@bus-elektronik.de>
---
This patch needs the [PATCH] AT91RM9200: real pointer variable
for PORT A to D configuration
By default the config use the old CONFIG_DRIVER_ETHER.
The patch supports also the new CONFIG_DRIVER_AT91EMAC
([PATCH] AT92RM9200 EMAC driver for NET MULTI API).
Remove comments in #define CONFIG_NET_MULTI line to use it.
Diffrence to V1:
* use the consistently silently board name eb_cpux9k2
* use I/O accessors
* dram_init using get_ram_size()
* remove non-standard data types
* no #defines in the middle of the code
* use global linker script
* remove undef's
* timeouts do not based on CONFIG_SYS_HZ
* fix several code style problems
* several fixes
diff --git a/MAINTAINERS b/MAINTAINERS
index d70a9d2..65b06e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -696,6 +696,10 @@ Steve Sakoman <sako...@gmail.com>
omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
+Jens Scharsig <e...@bus-elektronik.de>
+
+ eb_cpux9k2 ARM920T (AR91RM9200 SoC)
+
Robert Schwebel <r.schwe...@pengutronix.de>
csb226 xscale
diff --git a/MAKEALL b/MAKEALL
index d63c5c2..d7ef41c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -644,6 +644,7 @@ LIST_at91=" \
CPU9260 \
CPU9G20 \
csb637 \
+ eb_cpux9k2 \
kb9202 \
meesc \
mp2usb \
diff --git a/Makefile b/Makefile
index a69e6d5..d425b1a 100644
--- a/Makefile
+++ b/Makefile
@@ -2715,6 +2715,9 @@ CPUAT91_config : unconfig
csb637_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
+eb_cpux9k2_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t eb_cpux9k2 BuS at91rm9200
+
kb9202_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile
new file mode 100644
index 0000000..30e2f18
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := cpux9k2.o
+#led.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk
new file mode 100644
index 0000000..ff2cfd1
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
new file mode 100644
index 0000000..8e2737e
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <e...@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <lxt971a.h>
+
+unsigned int lxt972_IsPhyConnected(AT91PS_EMAC p_mac);
+uchar lxt972_GetLinkSpeed(AT91PS_EMAC p_mac);
+uchar lxt972_InitPhy(AT91PS_EMAC p_mac);
+uchar lxt972_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+
+#endif
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_VIDEO
+#include <bus_vcxk.h>
+
+extern unsigned long display_width;
+extern unsigned long display_height;
+#endif
+
+#ifdef CONFIG_CMD_NAND
+void cpux9k2_nand_hw_init(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* Correct IRDA resistor problem / Set PA23_TXD in Output */
+ writel(AT91C_PA23_TXD2, AT91C_PIOD_OER);
+
+ gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+#ifdef CONFIG_CMD_NAND
+ cpux9k2_nand_hw_init();
+#endif
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uchar mac[8];
+ uchar tm;
+ uchar midx;
+ uchar macn6, macn7;
+
+ if (getenv("ethaddr") == NULL) {
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *) &mac, sizeof(mac)) != 0) {
+ puts("Error reading MAC from EEPROM\n");
+ } else {
+ tm = 0;
+ macn6 = 0;
+ macn7 = 0xFF;
+ for (midx = 0; midx < 6; midx++) {
+ if ((mac[midx] != 0) && (mac[midx] != 0xFF))
+ tm++;
+ macn6 += mac[midx];
+ macn7 ^= mac[midx];
+ }
+ if ((macn6 != mac[6]) || (macn7 != mac[7]))
+ tm = 0;
+ if (tm) {
+ eth_setenv_enetaddr("ethaddr", mac);
+ } else {
+ puts("Error: invalid MAC at EEPROM\n");
+ }
+ }
+ }
+ gd->jt[XF_do_reset] = (void *) do_reset;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ udelay(10000);
+ eth_init(gd->bd);
+}
+#endif
+
+/*
+ * DRAM initialisations
+ */
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size =
+ get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+/*
+ * Ethernet initialisations
+ */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ rc = at91emac_register(bis, (ulong) AT91C_BASE_EMAC);
+ return rc;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * at91rm9200_GetPhyInterface
+ * Initialise the interface functions to the PHY
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = lxt972_InitPhy;
+ p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
+ p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
+ p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
+}
+
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define MASK_ALE (1 << 22) /* our ALE is AD22 */
+#define MASK_CLE (1 << 21) /* our CLE is AD21 */
+
+void cpux9k2_nand_hw_init(void)
+{
+ unsigned long csr;
+
+ /* Setup Smart Media, fitst enable the address range of CS3 */
+ writel(readl(AT91C_EBI_CSA) | AT91C_EBI_CS3A_SMC_SmartMedia,
+ AT91C_EBI_CSA);
+
+ /* RWH | RWS | TDF | NWS */
+ csr = (0x1 << 28) | (0x0 << 24) | (1 << 8) | 0x03 |
+ AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+ AT91C_SMC2_WSEN;
+ writel(csr, AT91C_SMC_CSR3);
+
+ writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR );
+ writel(AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE,
+ AT91C_PIOC_PDR);
+
+ /* Configure PC2 as input (signal Nand READY ) */
+ writel(AT91C_PC2_BFAVD, AT91C_PIOC_PER);
+ writel(AT91C_PC2_BFAVD, AT91C_PIOC_ODR); /* disable output */
+
+ /* PIOB and PIOC clock enabling */
+ writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
+ writel(AT91C_PIO_PC0, AT91C_PIOC_CODR);
+}
+
+static void board_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ if ((ctrl & NAND_NCE))
+ writel(AT91C_PIO_PC0, AT91C_PIOC_CODR);
+ else
+ writel(AT91C_PIO_PC0, AT91C_PIOC_SODR);
+
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int board_nand_dev_ready(struct mtd_info *mtd)
+{
+ return ((readl(AT91C_PIOC_PDSR) & AT91C_PIO_PC2) != 0);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ cpux9k2_nand_hw_init();
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = board_nand_hwcontrol;
+ nand->dev_ready = board_nand_dev_ready;
+ nand->chip_delay = 20;
+ return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * drv_video_init
+ * FUNCTION: initialize VCxK device
+ */
+
+int drv_video_init(void)
+{
+ char *s;
+ unsigned long splash;
+ unsigned long csr;
+
+ printf("Init Video as ");
+ s = getenv("displaywidth");
+ if (s != NULL)
+ display_width = simple_strtoul(s, NULL, 10);
+ else
+ display_width = 256;
+ s = getenv("displayheight");
+ if (s != NULL)
+ display_height = simple_strtoul(s, NULL, 10);
+ else
+ display_height = 256;
+ printf("%ld x %ld pixel matrix\n", display_width, display_height);
+
+ /* RWH | RWS | TDF | NWS */
+ csr = (0x7 << 28) | (0x7 << 24) | (15 << 8) | 0x7F |
+ AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_16 |
+ AT91C_SMC2_BAT | AT91C_SMC2_WSEN;
+ writel(csr, AT91C_SMC_CSR2);
+ writel(1 << AT91C_ID_PIOB, AT91C_PMC_PCER);
+
+ vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+ s = getenv("splashimage");
+ if (s != NULL) {
+ splash = simple_strtoul(s, NULL, 16);
+ printf("use splashimage: %lx\n", splash);
+ video_display_bitmap(splash, 0, 0);
+ }
+#endif
+ return 0;
+}
+#endif
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_STATUS_LED
+
+void __led_toggle(led_id_t mask)
+{
+ if (readl(AT91C_PIOD_ODSR) & mask)
+ writel(mask, AT91C_PIOD_CODR);
+ else
+ writel(mask, AT91C_PIOD_SODR);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ writel(1 << AT91C_ID_PIOD, AT91C_PMC_PCER); /* Enable PIOB clock */
+
+ /* Disable peripherals on LEDs */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, AT91C_PIOD_PER);
+ /* Enable pins as outputs */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, AT91C_PIOD_OER);
+ /* Turn all LEDs OFF */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, AT91C_PIOD_SODR);
+
+ __led_set(mask, state);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (state == STATUS_LED_ON)
+ writel(mask, AT91C_PIOD_CODR);
+ else
+ writel(mask, AT91C_PIOD_SODR);
+}
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rcode = 0;
+ ulong side;
+ ulong bright;
+
+ switch (argc) {
+ case 3:
+ side = simple_strtoul(argv[1], NULL, 10);
+ bright = simple_strtoul(argv[2], NULL, 10);
+ if ((side >= 0) && (side <= 3) &&
+ (bright >= 0) && (bright <= 1000)) {
+ vcxk_setbrightness(side, bright);
+ rcode = 0;
+ } else {
+ printf("parameters out of range\n");
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ }
+ break;
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ break;
+ }
+ return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+ bright, 3, 0, do_brightness,
+ "bright - sets the display brightness\n",
+ " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
+);
+
+/* EOF cpu9k2.c */
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
new file mode 100644
index 0000000..4463297
--- /dev/null
+++ b/include/configs/eb_cpux9k2.h
@@ -0,0 +1,426 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <e...@bus-elektronik.de>
+ *
+ * Configuation settings for the EB+CPUx9K2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_CPUx9K2_H_
+#define _CONFIG_EB_CPUx9K2_H_
+
+#include <asm/arch/hardware.h> /* needed for port definitions */
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
+#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
+#define USE_920T_MMU 1
+
+#define CONFIG_MISC_INIT_R
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
+#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
+
+
+#define CONFIG_BOOT_RETRY_TIME 30
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+/*
+ * ARM asynchronous clock
+ */
+
+#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4
WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
+#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * sdram
+ */
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ PHYS_SDRAM_SIZE - 0x00400000 - \
+ CONFIG_SYS_MALLOC_LEN)
+
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode
Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+/*
+ * Command line configuration
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_I2C_CMD_NO_FLAT
+#define CONFIG_I2C_CMD_TREE
+
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Filesystems
+ */
+
+#define CONFIG_JFFS2_NAND 1
+
+#ifndef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_OFFSET 0
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#else
+#define MTDIDS_DEFAULT "nor0=0,nand0=1"
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "0:" \
+ "384k(U-Boot)," \
+ "128k(Env)," \
+ "128k(Splash)," \
+ "4M(Kernel)," \
+ "-(FS)" \
+ ";" \
+ "1:" \
+ "-(jffs2)"
+#endif /* CONFIG_JFFS2_CMDLINE */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART/CONSOLE
+ */
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AT91RM9200_USART
+#define CONFIG_DBGU /* define DBGU as console */
+
+/*
+ * network
+ */
+
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_RESET_PHY_R 1
+
+/* #define CONFIG_NET_MULTI 1 */
+
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC 1
+#define CONFIG_DRIVER_AT91EMAC_QUIET 1
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+#define CONFIG_MII 1
+#else
+#define CONFIG_DRIVER_ETHER 1
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * I2C-Bus
+ */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C
+
+/* Software I2C driver configuration */
+
+#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
+#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
+
+#define I2C_INIT \
+ writel(1 << AT91C_ID_PIOA, AT91C_PMC_PCER); \
+ writel(AT91_PIN_SDA | AT91_PIN_SCL, AT91C_PIOA_IDR); \
+ writel(AT91_PIN_SDA | AT91_PIN_SCL, AT91C_PIOA_PUDR); \
+ writel(AT91_PIN_SDA | AT91_PIN_SCL, AT91C_PIOA_PER); \
+ writel(AT91_PIN_SDA | AT91_PIN_SCL, AT91C_PIOA_OER); \
+ writel(AT91_PIN_SDA | AT91_PIN_SCL, AT91C_PIOA_SODR);
+
+#define I2C_ACTIVE writel(AT91_PIN_SDA, AT91C_PIOA_MDDR);
+#define I2C_TRISTATE writel(AT91_PIN_SDA, AT91C_PIOA_MDER);
+#define I2C_READ ((readl(AT91C_PIOA_PDSR) & AT91_PIN_SDA) != 0)
+#define I2C_SDA(bit) \
+ if (bit) \
+ writel(AT91_PIN_SDA, AT91C_PIOA_SODR); \
+ else \
+ writel(AT91_PIN_SDA, AT91C_PIOA_CODR);
+
+#define I2C_SCL(bit) \
+ if (bit) \
+ writel(AT91_PIN_SCL, AT91C_PIOA_SODR); \
+ else \
+ writel(AT91_PIN_SCL, AT91C_PIOA_CODR);
+
+#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#endif /* CONFIG_HARD_I2C */
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+
+/* FLASH organization */
+
+/* NOR-FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main
flash */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
+
+/* NAND */
+
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+
+/* Status LED's */
+
+#define CONFIG_STATUS_LED 1
+#define CONFIG_BOARD_SPECIFIC_LED 1
+
+#define STATUS_LED_BOOT 1
+#define STATUS_LED_ACTIVE 0
+
+
+#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
+#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red
LED */
+#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
+
+#define CONFIG_VIDEO 1
+
+/* Options */
+
+#ifdef CONFIG_VIDEO
+
+#define CONFIG_VIDEO_VCXK 1
+
+#define CONFIG_SPLASH_SCREEN 1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
+#define CONFIG_SYS_VCXK_BASE 0x30000000
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT AT91C_BASE_PIOB
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR PIO_ODR
+
+#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
+#define CONFIG_SYS_VCXK_ENABLE_PORT AT91C_BASE_PIOB
+#define CONFIG_SYS_VCXK_ENABLE_DDR PIO_OER
+
+#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
+#define CONFIG_SYS_VCXK_REQUEST_PORT AT91C_BASE_PIOB
+#define CONFIG_SYS_VCXK_REQUEST_DDR PIO_OER
+
+#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
+#define CONFIG_SYS_VCXK_INVERT_PORT AT91C_BASE_PIOB
+#define CONFIG_SYS_VCXK_INVERT_DDR PIO_OER
+
+#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
+#define CONFIG_SYS_VCXK_RESET_PORT AT91C_BASE_PIOB
+#define CONFIG_SYS_VCXK_RESET_DDR PIO_OER
+
+#endif /* CONFIG_VIDEO */
+
+/* Environment */
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
+#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K
here */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTCOMMAND "run nfsboot"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "dhcp $(copy_addr) uImage_cpux9k2;" \
+ "run bootargsdefaults;" \
+ "set bootargs $(bootargs) boot=nfs " \
+ ";echo $(bootargs)" \
+ ";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "displaywidth=256\0" \
+ "displayheight=512\0" \
+ "displaybsteps=1023\0" \
+ "ubootaddr=10000000\0" \
+ "splashimage=10080000\0" \
+ "kerneladdr=100A0000\0" \
+ "kernelsize=00400000\0" \
+ "rootfsaddr=104A0000\0" \
+ "copy_addr=21200000\0" \
+ "rootfssize=00B60000\0" \
+ "bootargsdefaults=set bootargs " \
+ "console=ttyS0,115200 " \
+ "video=vcxk_fb:xres:${displaywidth}," \
+ "yres:${displayheight}," \
+ "bres:${displaybsteps} " \
+ "mem=62M " \
+ "panic=10 " \
+ "uboot=\\\"${ver}\\\" " \
+ "\0" \
+ "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
+ "dhcp $(copy_addr) uImage_cpux9k2;" \
+ "erase $(kerneladdr) +$(kernelsize);" \
+ "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
+ "protect on $(kerneladdr) +$(kernelsize)" \
+ "\0" \
+ "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
+ "dhcp $(copy_addr) rfs;" \
+ "erase $(rootfsaddr) +$(rootfssize);" \
+ "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
+ "\0" \
+ "update_uboot=protect off 10000000 1005FFFF;" \
+ "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
+ "erase 10000000 1005FFFF;" \
+ "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
+ "protect on 10000000 1005FFFF;reset\0" \
+ "update_splash=protect off $(splashimage) +20000;" \
+ "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
+ "erase $(splashimage) +20000;" \
+ "cp.b $(fileaddr) 10080000 $(filesize);" \
+ "protect on $(splashimage) +20000;reset\0" \
+ "emergency=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=emergency " \
+ ";bootm $(kerneladdr)\0" \
+ "netemergency=run bootargsdefaults;" \
+ "dhcp $(copy_addr) uImage_cpux9k2;" \
+ "set bootargs $(bootargs) root=initramfs boot=emergency " \
+ ";bootm $(copy_addr)\0" \
+ "norboot=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=local " \
+ ";bootm $(kerneladdr)\0" \
+ "nandboot=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=nand " \
+ ";bootm $(kerneladdr)\0" \
+ "uu=run update_uboot\0" \
+ "ur=run update_root;run nk\0" \
+ "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+ "boot=local " \
+ ";echo $(bootargs)" \
+ ";dhcp uImage_cpux9k2;bootm\0" \
+ "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+ "boot=nand " \
+ ";echo $(bootargs)" \
+ ";dhcp uImage_cpux9k2;bootm\0" \
+ " "
+
+/*--------------------------------------------------------------------------*/
+
+#endif
+
+/* EOF */
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