From: "eric.gao" <eric....@rock-chips.com>
Signed-off-by: eric.gao <eric....@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 33 ++
arch/arm/dts/rk3399.dtsi | 72 +++++
arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 2 +-
arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 203 +++++++++++++
arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
configs/evb-rk3399_defconfig | 4 +
drivers/video/Kconfig | 2 +
drivers/video/rockchip/Kconfig | 44 +++
drivers/video/rockchip/Makefile | 7 +-
drivers/video/rockchip/panel.c | 81 +++++
drivers/video/rockchip/rk_mipi.c | 371 +++++++++++++++++++++++
drivers/video/rockchip/rk_vop.c | 12 +-
12 files changed, 827 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
create mode 100644 drivers/video/rockchip/Kconfig
create mode 100644 drivers/video/rockchip/panel.c
create mode 100644 drivers/video/rockchip/rk_mipi.c
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 7a889c7..abb00e8 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -52,6 +52,10 @@
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
+ panel:panel {
+ compatible = "BOE,TV080WUM";
+ status = "disabled";
+ };
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
@@ -218,6 +222,35 @@
};
};
+&panel {
+ backlight_en = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ backlight_pwm = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vcc33_lcd>;
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+ display-timings {
+ timing0 {
+ bits-per-pixel = <24>;
+ clock-frequency = <160000000>;
+ hfront-porch = <120>;
+ hsync-len = <20>;
+ hback-porch = <21>;
+ hactive = <1200>;
+ vfront-porch = <21>;
+ vsync-len = <3>;
+ vback-porch = <18>;
+ vactive = <1920>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 93e3bf4..c82e674 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -667,6 +667,78 @@
status = "disabled";
};
+ vopl: vop@ff8f0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3399-vop-lit";
+ reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru
SRST_D_VOP1>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "okay";
+ vopl_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vopl_out_mipi: endpoint@0 {
+ reg = <3>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
+ };
+ };
+
+ vopb: vop@ff900000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3399-vop-big";
+ reg = <0x0 0xff900000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+ #clock-cells = <0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru
SRST_D_VOP0>;
+ reset-names = "axi", "ahb", "dclk";
+ /*power-domains = <&power RK3399_PD_VOPB>;*/
+ status = "okay";
+ vopb_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vopb_out_mipi: endpoint@0 {
+ reg = <3>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
+ };
+ };
+
+ mipi_dsi: mipi@ff960000 {
+ compatible = "rockchip,rk3399_mipi_dsi";
+ reg = <0x0 0xff960000 0x0 0x8000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_DPHY_TX0_CFG>;
+ clock-names = "ref", "pclk", "phy_cfg";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
pinctrl: pinctrl {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pinctrl";
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index cf830d0..8aa08d4 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -74,7 +74,7 @@ check_member(rk3399_cru, sdio1_con[1], 0x594);
#define OSC_HZ (24*MHz)
#define APLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
-#define CPLL_HZ (384*MHz)
+#define CPLL_HZ (594*MHz)
#define PPLL_HZ (676*MHz)
#define PMU_PCLK_HZ (48*MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
new file mode 100644
index 0000000..478cb21
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
+ * author: eric....@rock-chips.com
+ * create date: 2017-03-31
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef RK33_MIPI_DSI_H
+#define RK33_MIPI_DSI_H
+
+#define GRF_BASE 0xFF770000
+#define RK_GRF_CON20 0x06250
+#define RK_GRF_CON22 0x06258
+#define MHz 1000000
+
+#define MIPI_DSI_HOST0_BASE 0xff960000
+#define MIPI_DSI_HOST1_BASE 0xff968000
+
+/*
+ * function bits definition
+ * register addr | bits | offest
+ */
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+ ((addr<<16) | (bits<<8) | (bit_offset))
+
+/* DWC_DSI_VERSION_0X3133302A */
+#define VERSION DSI_HOST_BITS(0X000, 32, 0)
+#define SHUTDOWNZ DSI_HOST_BITS(0X004, 1, 0)
+#define TO_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 8)
+#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0X008, 8, 0)
+#define DPI_VCID DSI_HOST_BITS(0X00C, 2, 0)
+#define EN18_LOOSELY DSI_HOST_BITS(0X010, 1, 8)
+#define DPI_COLOR_CODING DSI_HOST_BITS(0X010, 4, 0)
+#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 4)
+#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 3)
+#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 2)
+#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 1)
+#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0X014, 1, 0)
+#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 16)
+#define INVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 0)
+#define CRC_RX_EN DSI_HOST_BITS(0X02C, 1, 4)
+#define ECC_RX_EN DSI_HOST_BITS(0X02C, 1, 3)
+#define BTA_EN DSI_HOST_BITS(0X02C, 1, 2)
+#define EOTP_RX_EN DSI_HOST_BITS(0X02C, 1, 1)
+#define EOTP_TX_EN DSI_HOST_BITS(0X02C, 1, 0)
+#define GEN_VID_RX DSI_HOST_BITS(0X030, 2, 0)
+#define CMD_VIDEO_MODE DSI_HOST_BITS(0X034, 1, 0)
+#define VPG_ORIENTATION DSI_HOST_BITS(0X038, 1, 24)
+#define VPG_MODE DSI_HOST_BITS(0X038, 1, 20)
+#define VPG_EN DSI_HOST_BITS(0X038, 1, 16)
+#define LP_CMD_EN DSI_HOST_BITS(0X038, 1, 15)
+#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0X038, 1, 14)
+#define LP_HFP_EN DSI_HOST_BITS(0X038, 1, 13)
+#define LP_HBP_EN DSI_HOST_BITS(0X038, 1, 12)
+#define LP_VACT_EN DSI_HOST_BITS(0X038, 1, 11)
+#define LP_VFP_EN DSI_HOST_BITS(0X038, 1, 10)
+#define LP_VBP_EN DSI_HOST_BITS(0X038, 1, 9)
+#define LP_VSA_EN DSI_HOST_BITS(0X038, 1, 8)
+#define VID_MODE_TYPE DSI_HOST_BITS(0X038, 2, 0)
+#define VID_PKT_SIZE DSI_HOST_BITS(0X03C, 14, 0)
+#define NUM_CHUNKS DSI_HOST_BITS(0X040, 13, 0)
+#define NULL_PKT_SIZE DSI_HOST_BITS(0X044, 13, 0)
+#define VID_HSA_TIME DSI_HOST_BITS(0X048, 12, 0)
+#define VID_HBP_TIME DSI_HOST_BITS(0X04C, 12, 0)
+#define VID_HLINE_TIME DSI_HOST_BITS(0X050, 15, 0)
+#define VID_VSA_LINES DSI_HOST_BITS(0X054, 10, 0)
+#define VID_VBP_LINES DSI_HOST_BITS(0X058, 10, 0)
+#define VID_VFP_LINES DSI_HOST_BITS(0X05C, 10, 0)
+#define VID_ACTIVE_LINES DSI_HOST_BITS(0X060, 14, 0)
+#define EDPI_CMD_SIZE DSI_HOST_BITS(0X064, 16, 0)
+#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0X068, 1, 24)
+#define DCS_LW_TX DSI_HOST_BITS(0X068, 1, 19)
+#define DCS_SR_0P_TX DSI_HOST_BITS(0X068, 1, 18)
+#define DCS_SW_1P_TX DSI_HOST_BITS(0X068, 1, 17)
+#define DCS_SW_0P_TX DSI_HOST_BITS(0X068, 1, 16)
+#define GEN_LW_TX DSI_HOST_BITS(0X068, 1, 14)
+#define GEN_SR_2P_TX DSI_HOST_BITS(0X068, 1, 13)
+#define GEN_SR_1P_TX DSI_HOST_BITS(0X068, 1, 12)
+#define GEN_SR_0P_TX DSI_HOST_BITS(0X068, 1, 11)
+#define GEN_SW_2P_TX DSI_HOST_BITS(0X068, 1, 10)
+#define GEN_SW_1P_TX DSI_HOST_BITS(0X068, 1, 9)
+#define GEN_SW_0P_TX DSI_HOST_BITS(0X068, 1, 8)
+#define ACK_RQST_EN DSI_HOST_BITS(0X068, 1, 1)
+#define TEAR_FX_EN DSI_HOST_BITS(0X068, 1, 0)
+#define GEN_WC_MSBYTE DSI_HOST_BITS(0X06C, 14, 16)
+#define GEN_WC_LSBYTE DSI_HOST_BITS(0X06C, 8, 8)
+#define GEN_VC DSI_HOST_BITS(0X06C, 2, 6)
+#define GEN_DT DSI_HOST_BITS(0X06C, 6, 0)
+#define GEN_PLD_DATA DSI_HOST_BITS(0X070, 32, 0)
+#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0X074, 1, 6)
+#define GEN_PLD_R_FULL DSI_HOST_BITS(0X074, 1, 5)
+#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0X074, 1, 4)
+#define GEN_PLD_W_FULL DSI_HOST_BITS(0X074, 1, 3)
+#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0X074, 1, 2)
+#define GEN_CMD_FULL DSI_HOST_BITS(0X074, 1, 1)
+#define GEN_CMD_EMPTY DSI_HOST_BITS(0X074, 1, 0)
+#define HSTX_TO_CNT DSI_HOST_BITS(0X078, 16, 16)
+#define LPRX_TO_CNT DSI_HOST_BITS(0X078, 16, 0)
+#define HS_RD_TO_CNT DSI_HOST_BITS(0X07C, 16, 0)
+#define LP_RD_TO_CNT DSI_HOST_BITS(0X080, 16, 0)
+#define PRESP_TO_MODE DSI_HOST_BITS(0X084, 1, 24)
+#define HS_WR_TO_CNT DSI_HOST_BITS(0X084, 16, 0)
+#define LP_WR_TO_CNT DSI_HOST_BITS(0X088, 16, 0)
+#define BTA_TO_CNT DSI_HOST_BITS(0X08C, 16, 0)
+#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0X094, 1, 1)
+#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0X094, 1, 0)
+#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 16)
+#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0X098, 10, 0)
+#define PHY_HS2LP_TIME DSI_HOST_BITS(0X09C, 8, 24)
+#define PHY_LP2HS_TIME DSI_HOST_BITS(0X09C, 8, 16)
+#define MAX_RD_TIME DSI_HOST_BITS(0X09C, 15, 0)
+#define PHY_FORCEPLL DSI_HOST_BITS(0X0A0, 1, 3)
+#define PHY_ENABLECLK DSI_HOST_BITS(0X0A0, 1, 2)
+#define PHY_RSTZ DSI_HOST_BITS(0X0A0, 1, 1)
+#define PHY_SHUTDOWNZ DSI_HOST_BITS(0X0A0, 1, 0)
+#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0X0A4, 8, 8)
+#define N_LANES DSI_HOST_BITS(0X0A4, 2, 0)
+#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0X0A8, 1, 3)
+#define PHY_TXREQULPSLAN DSI_HOST_BITS(0X0A8, 1, 2)
+#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0X0A8, 1, 1)
+#define PHY_TXREQULPSCLK DSI_HOST_BITS(0X0A8, 1, 0)
+#define PHY_TX_TRIGGERS DSI_HOST_BITS(0X0AC, 4, 0)
+#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0X0B0, 1, 2)
+#define PHYLOCK DSI_HOST_BITS(0X0B0, 1, 0)
+#define PHY_TESTCLK DSI_HOST_BITS(0X0B4, 1, 1)
+#define PHY_TESTCLR DSI_HOST_BITS(0X0B4, 1, 0)
+#define PHY_TESTEN DSI_HOST_BITS(0X0B8, 1, 16)
+#define PHY_TESTDOUT DSI_HOST_BITS(0X0B8, 8, 8)
+#define PHY_TESTDIN DSI_HOST_BITS(0X0B8, 8, 0)
+#define PHY_TEST_CTRL1 DSI_HOST_BITS(0X0B8, 17, 0)
+#define PHY_TEST_CTRL0 DSI_HOST_BITS(0X0B4, 2, 0)
+#define INT_ST0 DSI_HOST_BITS(0X0BC, 21, 0)
+#define INT_ST1 DSI_HOST_BITS(0X0C0, 18, 0)
+#define INT_MKS0 DSI_HOST_BITS(0X0C4, 21, 0)
+#define INT_MKS1 DSI_HOST_BITS(0X0C8, 18, 0)
+#define INT_FORCE0 DSI_HOST_BITS(0X0D8, 21, 0)
+#define INT_FORCE1 DSI_HOST_BITS(0X0DC, 18, 0)
+
+#define code_hs_rx_clock 0x34
+#define code_hs_rx_lane0 0x44
+#define code_hs_rx_lane1 0x54
+#define code_hs_rx_lane2 0x84
+#define code_hs_rx_lane3 0x94
+
+#define code_pll_input_div_rat 0x17
+#define code_pll_loop_div_rat 0x18
+#define code_pll_vcorange_vcocap 0x10
+#define code_pll_input_loop_div_rat 0x19
+#define code_pll_cpctrl 0x11
+
+#define code_hstxdatalanerequsetstatetime 0x70
+#define code_hstxdatalanepreparestatetime 0x71
+#define code_hstxdatalanehszerostatetime 0x72
+
+enum vid_mode_type_enum {
+ NON_BURST_SYNC_PLUSE = 0,
+ NON_BURST_SYNC_EVENT,
+ BURST_MODE,
+};
+
+enum cmd_video_mode {
+ VIDEO_MODE = 0,
+ CMD_MODE,
+};
+
+enum dpi_color_coding {
+ DPI_16BIT_CFG_1 = 0,
+ DPI_16BIT_CFG_2,
+ DPI_16BIT_CFG_3,
+ DPI_18BIT_CFG_1,
+ DPI_18BIT_CFG_2,
+ DPI_24BIT,
+ DPI_20BIT_YCBCR_422_LP,
+ DPI_24BIT_YCBCR_422,
+ DPI_16BIT_YCBCR_422,
+ DPI_30BIT,
+ DPI_36BIT,
+ DPI_12BIT_YCBCR_420,
+};
+
+enum vop_id {
+ VOP_B = 0,
+ VOP_L,
+};
+
+/*
+ * Name :rk_write_reg(reg,val)
+ *
+ * reg: register name from the above define file,it contain the addr,
+ * bits number and bits offset
+ * val: reg value that will be writen to register, it can't be over
+ * the real bit num limit, For example, TO_CLK_DIVISION have 8
+ * bits space, so it's value can't great than 255
+ */
+#define GET_VAL(reg, val) ((val & (~(0xffffffff << ((reg & 0xffff) >> 8)))) \
+ << (reg&0xff)) | ((readl((reg >> 16)+MIPI_DSI_HOST0_BASE)) & \
+ (~((0xffffffff<<(reg&0xff))&(0xffffffff>>\
+ (32-(reg&0xff)-((reg>>8)&0xff))))))
+#define GET_ADDR(reg) (reg >> 16)+MIPI_DSI_HOST0_BASE
+#define rk_write_reg(reg, val) writel(GET_VAL(reg, val), GET_ADDR(reg));
+
+#endif /* end of RK33_MIPI_DSI_H */
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 0ce3d67..d5599ec 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -90,6 +90,7 @@ enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
VOP_MODE_LVDS,
+ VOP_MODE_MIPI,
VOP_MODE_NONE,
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index aac6d2d..b9cb0e8 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -64,3 +64,7 @@ CONFIG_PMIC_CHILDREN=y
CONFIG_SPL_PMIC_CHILDREN=y
CONFIG_PMIC_RK808=y
CONFIG_REGULATOR_RK808=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_MIPI=y
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2069576..4b03a9a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -405,6 +405,8 @@ config VIDEO_ROCKCHIP
(DSI). This driver supports the on-chip video output device, and
targets the Rockchip RK3288.
+source "drivers/video/rockchip/Kconfig"
+
config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
depends on SANDBOX
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
new file mode 100644
index 0000000..72473f6
--- /dev/null
+++ b/drivers/video/rockchip/Kconfig
@@ -0,0 +1,44 @@
+#
+# video drivers configuration
+# for rockchip soc
+#
+
+menu "Video Display Port Select"
+
+config DISPLAY_MIPI
+ bool "MIPI Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ Select MIPI dsi for video port.
+ if you want to enable these function,you need
+ to turn on the DM_VIDEO,VDEIO_ROCKCHIP together
+ what is more,you shoud also enable the related
+ power,such as lcd3v3, lcd1v8,lcd1v0 and so on.
+config DISPLAY_EDP
+ bool "EDP Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ Select EDP for video port.
+ if you want to enable these function,you need
+ to turn on the DM_VIDEO,VDEIO_ROCKCHIP together
+ what is more,you shoud also enable the related
+ power,such as lcd3v3, lcd1v8,lcd1v0 and so on.
+config DISPLAY_LVDS
+ bool "LVDS Port"
+ depends on VIDEO_ROCKCHIP
+ help
+ Select LVDS for video port.
+ if you want to enable these function,you need
+ to turn on the DM_VIDEO,VDEIO_ROCKCHIP together
+ what is more,you shoud also enable the related
+ power,such as lcd3v3, lcd1v8,lcd1v0 and so on.
+config DISPLAY_HDMI
+ bool "HDMI port"
+ depends on VIDEO_ROCKCHIP
+ help
+ Select HDMI for video port
+ if you want to enable these function,you need
+ to turn on the DM_VIDEO,VDEIO_ROCKCHIP together
+ what is more,you shoud also enable the related
+ power,such as lcd3v3, lcd1v8,lcd1v0 and so on.
+endmenu
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 7962f86..98b26ea 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -5,4 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
+obj-$(CONFIG_VIDEO_ROCKCHIP) += rk_vop.o
+obj-$(CONFIG_VIDEO_ROCKCHIP) += panel.o
+obj-$(CONFIG_DISPLAY_MIPI) += rk_mipi.o
+obj-$(CONFIG_DISPLAY_EDP) += rk_edp.o
+obj-$(CONFIG_DISPLAY_LVDS) += rk_lvds.o
+obj-$(CONFIG_DISPLAY_HDMI) += rk_hdmi.o
diff --git a/drivers/video/rockchip/panel.c b/drivers/video/rockchip/panel.c
new file mode 100644
index 0000000..8b02b0f
--- /dev/null
+++ b/drivers/video/rockchip/panel.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <edid.h>
+#include <panel.h>
+#include <asm/hardware.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/mipi_rk3399.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3288.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int bind(struct udevice *dev)
+{
+ debug("Panel bind@%s_Line:%d\n", __func__, __LINE__);
+ return 0;
+}
+
+static int probe(struct udevice *dev)
+{
+ debug("Panel probe@%s_Line:%d\n", __func__, __LINE__);
+ return 0;
+}
+
+int rk_panel_enable_backlight(struct udevice *dev)
+{
+ struct gpio_desc bg_en, bg_pwm;
+ int node;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "BOE,TV080WUM");
+ if (node < 0) {
+ debug("Can't find node@%s_Line:%d\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ gpio_request_by_name_nodev(gd->fdt_blob, node, "backlight_en",
+ 0, &bg_en, GPIOD_IS_OUT);
+ gpio_request_by_name_nodev(gd->fdt_blob, node,
+ "backlight_pwm", 0, &bg_pwm, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&bg_en)) {
+ dm_gpio_set_value(&bg_en, 1);
+ dm_gpio_set_value(&bg_pwm, 1);
+ } else {
+ debug("GPIO Invalid@%s_Line:%d\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct panel_ops rk_panel_ops = {
+ .enable_backlight = rk_panel_enable_backlight,
+};
+
+static const struct udevice_id rk_panel_ids[] = {
+ { .compatible = "BOE,TV080WUM" },
+ { }
+};
+
+U_BOOT_DRIVER(rk_panel) = {
+ .name = "rk_panel",
+ .id = UCLASS_PANEL,
+ .of_match = rk_panel_ids,
+ .bind = bind,
+ .probe = probe,
+ .ops = &rk_panel_ops,
+};
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
new file mode 100644
index 0000000..84cfb96
--- /dev/null
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <panel.h>
+#include <asm/hardware.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/mipi_rk3399.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3288.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mipi_dsi {
+ u32 ref_clk;
+ u32 sys_clk;
+ u32 pix_clk;
+ u32 phy_clk;
+ u32 txbyte_clk;
+ u32 txesc_clk;
+};
+
+int rk_mipi_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+ if (fdtdec_decode_display_timing
+ (gd->fdt_blob, dev_of_offset(dev), 0, timing)) {
+ debug("%s: Failed to decode display timing\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int rk_mipi_dsi_enable(struct udevice *dev, struct mipi_dsi *mipi,
+ const struct display_timing *timing)
+{
+ int node, timing_node;
+ int val;
+ struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ u32 txbyte_clk = mipi->txbyte_clk;
+ u32 txesc_clk = mipi->txesc_clk;
+
+ txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
+
+ /* Select the video source */
+ switch (disp_uc_plat->source_id) {
+ case VOP_B:
+ val = 0x1 << 16 | 0x0;
+ writel(val, GRF_BASE+RK_GRF_CON20);
+ break;
+ case VOP_L:
+ val = 0x1 << 16 | 0x1;
+ writel(val, GRF_BASE+RK_GRF_CON20);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Set Controller as TX mode */
+ val = 0x1 << 28 | 0x0 << 12;
+ val |= 0xf << 20 | 0x0 << 4;
+ val |= 0xf << 16 | 0x0;
+ writel(val, GRF_BASE+RK_GRF_CON22);
+
+ /* Set Display timing parameter */
+ rk_write_reg(VID_HSA_TIME, timing->hsync_len.typ);
+ rk_write_reg(VID_HBP_TIME, timing->hback_porch.typ);
+ rk_write_reg(VID_HLINE_TIME,
+ (timing->hsync_len.typ +
+ timing->hback_porch.typ +
+ timing->hactive.typ +
+ timing->hfront_porch.typ));
+ rk_write_reg(VID_VSA_LINES, timing->vsync_len.typ);
+ rk_write_reg(VID_VBP_LINES, timing->vback_porch.typ);
+ rk_write_reg(VID_VFP_LINES, timing->vfront_porch.typ);
+ rk_write_reg(VID_ACTIVE_LINES, timing->vactive.typ);
+
+ /* Set Signal Polarity */
+ val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
+ rk_write_reg(HSYNC_ACTIVE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
+ rk_write_reg(VSYNC_ACTIVE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
+ rk_write_reg(DISPLAY_FLAGS_DE_LOW, val);
+
+ val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
+ rk_write_reg(COLORM_ACTIVE_LOW, val);
+
+ /* Set video mode */
+ rk_write_reg(CMD_VIDEO_MODE, VIDEO_MODE);
+
+ /* Set video mode transmission type as burst mode */
+ rk_write_reg(VID_MODE_TYPE, BURST_MODE);
+
+ /* Set pix num in a video package */
+ rk_write_reg(VID_PKT_SIZE, 0x4b0);
+
+ /* Set dpi color coding depth 24 bit */
+ timing_node = fdt_subnode_offset(gd->fdt_blob,
+ dev_of_offset(dev), "display-timings");
+ node = fdt_first_subnode(gd->fdt_blob, timing_node);
+ val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
+ switch (val) {
+ case 16:
+ rk_write_reg(DPI_COLOR_CODING, DPI_16BIT_CFG_1);
+ break;
+ case 24:
+ rk_write_reg(DPI_COLOR_CODING, DPI_24BIT);
+ break;
+ case 30:
+ rk_write_reg(DPI_COLOR_CODING, DPI_30BIT);
+ break;
+ default:
+ rk_write_reg(DPI_COLOR_CODING, DPI_24BIT);
+ }
+ /* Enable low power mode */
+ rk_write_reg(LP_CMD_EN, 1);
+ rk_write_reg(LP_HFP_EN, 1);
+ rk_write_reg(LP_VACT_EN, 1);
+ rk_write_reg(LP_VFP_EN, 1);
+ rk_write_reg(LP_VBP_EN, 1);
+ rk_write_reg(LP_VSA_EN, 1);
+
+ /* Division for timeout counter clk */
+ rk_write_reg(TO_CLK_DIVISION, 0x0a);
+
+ /* Tx esc clk division from txbyte clk */
+ rk_write_reg(TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
+
+ /*
+ * Timeout count for hs<->lp
+ * transation between Line period
+ */
+ rk_write_reg(HSTX_TO_CNT, 0x3e8);
+
+ /* Phy State transfer timing */
+ rk_write_reg(PHY_STOP_WAIT_TIME, 32);
+ rk_write_reg(PHY_TXREQUESTCLKHS, 1);
+ rk_write_reg(PHY_HS2LP_TIME, 0x14);
+ rk_write_reg(PHY_LP2HS_TIME, 0x10);
+ rk_write_reg(MAX_RD_TIME, 0x2710);
+
+ /* Power on */
+ rk_write_reg(SHUTDOWNZ, 1);
+
+ return 0;
+}
+
+/*
+ * rk mipi dphy write function
+ */
+static void rk_mipi_phy_write(unsigned char test_code,
+ unsigned char *test_data,
+ unsigned char size)
+{
+ int i = 0;
+ /* Write Test code */
+ rk_write_reg(PHY_TESTCLK, 1);
+ rk_write_reg(PHY_TESTDIN, test_code);
+ rk_write_reg(PHY_TESTEN, 1);
+ rk_write_reg(PHY_TESTCLK, 0);
+ rk_write_reg(PHY_TESTEN, 0);
+
+ /* Write Test data */
+ for (i = 0; i < size; i++) {
+ rk_write_reg(PHY_TESTCLK, 0);
+ rk_write_reg(PHY_TESTDIN, test_data[i]);
+ rk_write_reg(PHY_TESTCLK, 1);
+ }
+}
+
+/*
+ * mipi dphy config function. calculate the suitable prediv,
+ * feedback div,fsfreqrang value ,cap ,lpf and so on
+ * according to the given pix clk ratthe.and then enable phy
+ */
+static int rk_mipi_phy_enable(struct mipi_dsi *mipi)
+{
+ int i;
+ u64 fbdiv;
+ u64 prediv = 1;
+ u64 ddr_clk = mipi->phy_clk;
+ u32 refclk = mipi->ref_clk;
+ u32 remain = refclk;
+ unsigned char test_data[2] = {0};
+
+ /* dphy fsfreqrang */
+ int rang[39][2] = {
+ {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
+ {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
+ {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
+ {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
+ {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
+ {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
+ {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
+ {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
+ {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
+ {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} };
+
+ /* Shutdown mode */
+ rk_write_reg(PHY_SHUTDOWNZ, 0);
+ rk_write_reg(PHY_RSTZ, 0);
+ rk_write_reg(PHY_TESTCLR, 1);
+ mdelay(10);
+ /* Pll locking */
+ rk_write_reg(PHY_TESTCLR, 0);
+ mdelay(10);
+
+ /* config cp and lfp */
+ test_data[0] = 0x80 | (ddr_clk / (200*MHz)) << 3 | 0x3;
+ rk_mipi_phy_write(0x10, test_data, 1);
+
+ test_data[0] = 0x8;
+ rk_mipi_phy_write(0x11, test_data, 1);
+
+ test_data[0] = 0x80 | 0x40;
+ rk_mipi_phy_write(0x12, test_data, 1);
+
+ /* select the suitable value for fsfreqrang reg */
+ for (i = 0; i < 39; i++) {
+ if (ddr_clk / (MHz) >= rang[i][0])
+ break;
+ }
+ test_data[0] = rang[i][1] << 1;
+ rk_mipi_phy_write(code_hs_rx_lane0, test_data, 1);
+ /*
+ * Calculate the best ddrclk and it's
+ * corresponding div value, If the given
+ * pixelclock is great than 250M, the ddr
+ * clk will be fix 1500M.otherwise , it's
+ * equal to ddr_clk= pixclk*6.
+ */
+ for (i = 1; i < 6; i++) {
+ if ((ddr_clk * i % refclk < remain) &&
+ (ddr_clk * i / refclk) < 512) {
+ prediv = i;
+ remain = ddr_clk * i % refclk;
+ }
+ }
+ fbdiv = ddr_clk * prediv / refclk;
+ ddr_clk = refclk * fbdiv / prediv;
+ mipi->phy_clk = ddr_clk;
+ /* config prediv and feedback reg */
+ test_data[0] = prediv - 1;
+ rk_mipi_phy_write(code_pll_input_div_rat, test_data, 1);
+ mdelay(2);
+ test_data[0] = (fbdiv - 1) & 0x1f;
+ rk_mipi_phy_write(code_pll_loop_div_rat, test_data, 1);
+ mdelay(2);
+ test_data[0] = (fbdiv - 1) >> 5 | 0x80;
+ rk_mipi_phy_write(code_pll_loop_div_rat, test_data, 1);
+ mdelay(2);
+ test_data[0] = 0x30;
+ rk_mipi_phy_write(code_pll_input_loop_div_rat, test_data, 1);
+ mdelay(2);
+
+ /* rest config */
+ test_data[0] = 0x4d;
+ rk_mipi_phy_write(0x20, test_data, 1);
+
+ test_data[0] = 0x3d;
+ rk_mipi_phy_write(0x21, test_data, 1);
+
+ test_data[0] = 0xdf;
+ rk_mipi_phy_write(0x21, test_data, 1);
+
+ test_data[0] = 0x7;
+ rk_mipi_phy_write(0x22, test_data, 1);
+
+ test_data[0] = 0x80 | 0x7;
+ rk_mipi_phy_write(0x22, test_data, 1);
+
+ test_data[0] = 0x80 | 15;
+ rk_mipi_phy_write(code_hstxdatalanerequsetstatetime,
+ test_data, 1);
+ test_data[0] = 0x80 | 85;
+ rk_mipi_phy_write(code_hstxdatalanepreparestatetime,
+ test_data, 1);
+ test_data[0] = 0x40 | 10;
+ rk_mipi_phy_write(code_hstxdatalanehszerostatetime,
+ test_data, 1);
+ /* enter into stop mode */
+ rk_write_reg(N_LANES, 0x03);
+ rk_write_reg(PHY_ENABLECLK, 1);
+ mdelay(10);
+ rk_write_reg(PHY_FORCEPLL, 1);
+ mdelay(10);
+ rk_write_reg(PHY_SHUTDOWNZ, 1);
+ mdelay(10);
+ rk_write_reg(PHY_RSTZ, 1);
+ mdelay(10);
+
+ return 0;
+}
+
+static int enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing)
+{
+ struct udevice *panel;
+ /* Check if there are avalble panel */
+ if (uclass_first_device(UCLASS_PANEL, &panel)) {
+ debug("No panel found@%s_LINE:%d\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ return panel_enable_backlight(panel);
+}
+
+/*
+ * probe function: check panel existence and reading
+ * it's timing. then config mipi dsi controller and
+ * enable it according to the timing parameter
+ */
+static int probe(struct udevice *dev)
+{
+ struct display_timing timing;
+ struct mipi_dsi mipi;
+
+ /* Read panel timing,and save to struct timing */
+ rk_mipi_read_timing(dev, &timing);
+
+ /* fill the mipi controller parameter */
+ mipi.ref_clk = 24*MHz;
+ mipi.sys_clk = mipi.ref_clk;
+ mipi.pix_clk = timing.pixelclock.typ;
+ mipi.phy_clk = mipi.pix_clk * 6;
+ mipi.txbyte_clk = mipi.phy_clk / 8;
+ mipi.txesc_clk = 20*MHz;
+
+ /* config mipi dsi according to timing and enable it */
+ rk_mipi_dsi_enable(dev, &mipi, &timing);
+
+ /* init mipi dsi phy */
+ rk_mipi_phy_enable(&mipi);
+
+ return 0;
+}
+
+static const struct dm_display_ops rk_mipi_dsi_ops = {
+ .read_timing = rk_mipi_read_timing,
+ .enable = enable,
+};
+
+static const struct udevice_id rk_mipi_dsi_ids[] = {
+ { .compatible = "rockchip,rk3399_mipi_dsi" },
+ { }
+};
+
+U_BOOT_DRIVER(rk_mipi_dsi) = {
+ .name = "rk_mipi_dsi",
+ .id = UCLASS_DISPLAY,
+ .of_match = rk_mipi_dsi_ids,
+ .probe = probe,
+ .ops = &rk_mipi_dsi_ops,
+};
+
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index aeecb58..1de00f1 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -109,6 +109,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
V_HDMI_OUT_EN(1));
break;
+ case VOP_MODE_MIPI:
+ clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
+ V_MIPI_OUT_EN(1));
+ break;
case VOP_MODE_EDP:
default:
clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
@@ -245,7 +249,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
ret = clk_get_by_index(dev, 1, &clk);
if (!ret)
ret = clk_set_rate(&clk, timing.pixelclock.typ);
- if (ret) {
+ if (!ret) {
debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
return ret;
}
@@ -327,7 +331,7 @@ static int rk_vop_probe(struct udevice *dev)
for (node = fdt_first_subnode(blob, port);
node > 0;
node = fdt_next_subnode(blob, node)) {
- ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
+ ret = rk_display_init(dev, plat->base, VIDEO_BPP32, node);
if (ret)
debug("Device failed: ret=%d\n", ret);
if (!ret)
@@ -342,7 +346,7 @@ static int rk_vop_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- plat->size = 1920 * 1080 * 2;
+ plat->size = 1920 * 1200 * 4;
return 0;
}
@@ -351,6 +355,8 @@ static const struct video_ops rk_vop_ops = {
};
static const struct udevice_id rk_vop_ids[] = {
+ { .compatible = "rockchip,rk3399-vop-big" },
+ { .compatible = "rockchip,rk3399-vop-lit" },
{ .compatible = "rockchip,rk3288-vop" },
{ }
};
--
1.9.1
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