Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com

The DA8xx devices are similar to DaVinci devices but have a differing
memory map and updated peripheral versions.

Signed-off-by: Nick Thompson <nick.thomp...@gefanuc.com>
---
Applies to u-boot-ti

diff --git a/include/asm-arm/arch-davinci/hardware.h 
b/include/asm-arm/arch-davinci/hardware.h
index acf12ea..3071384 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -36,9 +36,10 @@
 #include <config.h>
 #include <asm/sizes.h>
 
+/* required by davinci drivers */
 #define        REG(addr)       (*(volatile unsigned int *)(addr))
-#define REG_P(addr)    ((volatile unsigned int *)(addr))
 
+/* required by davinci drivers */
 typedef volatile unsigned int  dv_reg;
 typedef volatile unsigned int *        dv_reg_p;
 
@@ -49,6 +50,8 @@ typedef volatile unsigned int *       dv_reg_p;
  * on other DaVinci chips.  Double check them before you try
  * using the addresses ... or PSC module identifiers, etc.
  */
+#ifndef CONFIG_SOC_DA8XX
+
 #define DAVINCI_DMA_3PCC_BASE                  (0x01c00000)
 #define DAVINCI_DMA_3PTC0_BASE                 (0x01c10000)
 #define DAVINCI_DMA_3PTC1_BASE                 (0x01c10400)
@@ -116,10 +119,61 @@ typedef volatile unsigned int *   dv_reg_p;
 
 #endif
 
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE                     0x01c42000
+#define DAVINCI_UART1_BASE                     0x01d0c000
+#define DAVINCI_UART2_BASE                     0x01d0d000
+#define DAVINCI_I2C0_BASE                      0x01c22000
+#define DAVINCI_I2C1_BASE                      0x01e28000
+#define DAVINCI_TIMER0_BASE                    0x01c20000
+#define DAVINCI_TIMER1_BASE                    0x01c21000
+#define DAVINCI_WDOG_BASE                      0x01c21000
+#define DAVINCI_PLL_CNTRL0_BASE                        0x01c11000
+#define DAVINCI_PSC0_BASE                      0x01c10000
+#define DAVINCI_PSC1_BASE                      0x01e27000
+#define DAVINCI_SPI0_BASE                      0x01c41000
+#define DAVINCI_USB_OTG_BASE                   0x01e00000
+#define DAVINCI_SPI1_BASE                      0x01e12000
+#define DAVINCI_GPIO_BASE                      0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE           0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE   0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE          0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE           0x01e24000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE          0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE       0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE       0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE       0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE       0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE       0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE             0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE             0xc0000000
+#define DAVINCI_INTC_BASE                      0xfffee000
+#define DAVINCI_BOOTCFG_BASE                   0x01c14000
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifdef CONFIG_SOC_DA8XX
+
+/* Clock IDs */
+#define DAVINCI_PLLM_CLKID                     (0xFF + 0)
+#define DAVINCI_PLLC_CLKID                     (0xFF + 1)
+#define DAVINCI_AUXCLK_CLKID                   (0xFF + 2)
+#define DAVINCI_MDIO_CLKID                     4
+#define DAVINCI_SPI0_CLKID                     2
+#define DAVINCI_UART2_CLKID                    2
+#define DAVINCI_ARM_CLKID                      6
+
+int clk_get(unsigned int id);
+
+#endif /* CONFIG_SOC_DA8XX */
+
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN         0
 #define DAVINCI_GPSC_DSPDOMAIN         1
 
+#ifndef CONFIG_SOC_DA8XX
+
 #define DAVINCI_LPSC_VPSSMSTR          0
 #define DAVINCI_LPSC_VPSSSLV           1
 #define DAVINCI_LPSC_TPCC              2
@@ -166,6 +220,52 @@ typedef volatile unsigned int *    dv_reg_p;
 #define DAVINCI_DM646X_LPSC_UART0      26
 #define DAVINCI_DM646X_LPSC_I2C                31
 
+#else /* CONFIG_SOC_DA8XX */
+
+/* LPSCs in PSC0 */
+#define DAVINCI_LPSC_TPCC              0
+#define DAVINCI_LPSC_TPTC0             1
+#define DAVINCI_LPSC_TPTC1             2
+#define DAVINCI_LPSC_AEMIF             3
+#define DAVINCI_LPSC_SPI0              4
+#define DAVINCI_LPSC_MMC_SD            5
+#define DAVINCI_LPSC_AINTC             6
+#define DAVINCI_LPSC_ARM_RAM_ROM       7
+#define DAVINCI_LPSC_SECCTL_KEYMGR     8
+#define DAVINCI_LPSC_UART0             9
+#define DAVINCI_LPSC_SCR0              10
+#define DAVINCI_LPSC_SCR1              11
+#define DAVINCI_LPSC_SCR2              12
+#define DAVINCI_LPSC_DMAX              13
+#define DAVINCI_LPSC_ARM               14
+#define DAVINCI_LPSC_GEM               15
+
+/* for LPSCs in PSC1, 32 + actual id is being used for differentiation */
+#define DAVINCI_LPSC_BASE      32
+#define DAVINCI_LPSC_USB11     (DAVINCI_LPSC_BASE + 1)
+#define DAVINCI_LPSC_USB20     (DAVINCI_LPSC_BASE + 2)
+#define DAVINCI_LPSC_GPIO      (DAVINCI_LPSC_BASE + 3)
+#define DAVINCI_LPSC_UHPI      (DAVINCI_LPSC_BASE + 4)
+#define DAVINCI_LPSC_EMAC      (DAVINCI_LPSC_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF  (DAVINCI_LPSC_BASE + 6)
+#define DAVINCI_LPSC_McASP0    (DAVINCI_LPSC_BASE + 7)
+#define DAVINCI_LPSC_McASP1    (DAVINCI_LPSC_BASE + 8)
+#define DAVINCI_LPSC_McASP2    (DAVINCI_LPSC_BASE + 9)
+#define DAVINCI_LPSC_SPI1      (DAVINCI_LPSC_BASE + 10)
+#define DAVINCI_LPSC_I2C1      (DAVINCI_LPSC_BASE + 11)
+#define DAVINCI_LPSC_UART1     (DAVINCI_LPSC_BASE + 12)
+#define DAVINCI_LPSC_UART2     (DAVINCI_LPSC_BASE + 13)
+#define DAVINCI_LPSC_LCDC      (DAVINCI_LPSC_BASE + 16)
+#define DAVINCI_LPSC_ePWM      (DAVINCI_LPSC_BASE + 17)
+#define DAVINCI_LPSC_eCAP      (DAVINCI_LPSC_BASE + 20)
+#define DAVINCI_LPSC_eQEP      (DAVINCI_LPSC_BASE + 21)
+#define DAVINCI_LPSC_SCR_P0    (DAVINCI_LPSC_BASE + 22)
+#define DAVINCI_LPSC_SCR_P1    (DAVINCI_LPSC_BASE + 23)
+#define DAVINCI_LPSC_CR_P3     (DAVINCI_LPSC_BASE + 26)
+#define DAVINCI_LPSC_L3_CBA_RAM        (DAVINCI_LPSC_BASE + 31)
+
+#endif /* CONFIG_SOC_DA8XX */
+
 void lpsc_on(unsigned int id);
 void dsp_on(void);
 
@@ -174,6 +274,8 @@ void davinci_enable_emac(void);
 void davinci_enable_i2c(void);
 void davinci_errata_workarounds(void);
 
+#ifndef CONFIG_SOC_DA8XX
+
 /* Some PSC defines */
 #define PSC_CHP_SHRTSW                 (0x01c40038)
 #define PSC_GBLCTL                     (0x01c41010)
@@ -194,6 +296,22 @@ void davinci_errata_workarounds(void);
 
 #define PSC_SILVER_BULLET              (0x01c41a20)
 
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC0_MDCTL             (DAVINCI_PSC0_BASE + 0xa00)
+#define PSC0_MDSTAT            (DAVINCI_PSC0_BASE + 0x800)
+#define PSC0_PTCMD             (DAVINCI_PSC0_BASE + 0x120)
+#define PSC0_PTSTAT            (DAVINCI_PSC0_BASE + 0x128)
+
+#define PSC1_MDCTL             (DAVINCI_PSC1_BASE + 0xa00)
+#define PSC1_MDSTAT            (DAVINCI_PSC1_BASE + 0x800)
+#define PSC1_PTCMD             (DAVINCI_PSC1_BASE + 0x120)
+#define PSC1_PTSTAT            (DAVINCI_PSC1_BASE + 0x128)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifndef CONFIG_SOC_DA8XX
+
 /* Miscellania... */
 #define VBPR                           (0x20000020)
 
@@ -206,4 +324,75 @@ void davinci_errata_workarounds(void);
 #define PINMUX3                                0x01c4000c
 #define PINMUX4                                0x01c40010
 
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifdef CONFIG_SOC_DA8XX
+
+/* Some PLL defines */
+#define PLL0_PLLCTL            (DAVINCI_PLL_CNTRL0_BASE + 0x100)
+#define PLL0_PLLM              (DAVINCI_PLL_CNTRL0_BASE + 0x110)
+#define PLL0_PREDIV            (DAVINCI_PLL_CNTRL0_BASE + 0x114)
+#define PLL0_POSTDIV           (DAVINCI_PLL_CNTRL0_BASE + 0x128)
+#define PLL0_DIV1              (DAVINCI_PLL_CNTRL0_BASE + 0x118)
+#define PLL0_DIV2              (DAVINCI_PLL_CNTRL0_BASE + 0x11c)
+#define PLL0_DIV3              (DAVINCI_PLL_CNTRL0_BASE + 0x120)
+#define PLL0_DIV4              (DAVINCI_PLL_CNTRL0_BASE + 0x160)
+#define PLL0_DIV5              (DAVINCI_PLL_CNTRL0_BASE + 0x164)
+#define PLL0_DIV6              (DAVINCI_PLL_CNTRL0_BASE + 0x168)
+#define PLL0_DIV7              (DAVINCI_PLL_CNTRL0_BASE + 0x16c)
+#define PLL0_DIV8              (DAVINCI_PLL_CNTRL0_BASE + 0x170)
+#define PLL0_DIV9              (DAVINCI_PLL_CNTRL0_BASE + 0x114)
+
+/* Boot config */
+#define PINMUX0                        (DAVINCI_BOOTCFG_BASE + 0x120)
+#define PINMUX1                        (DAVINCI_BOOTCFG_BASE + 0x124)
+#define PINMUX2                        (DAVINCI_BOOTCFG_BASE + 0x128)
+#define PINMUX3                        (DAVINCI_BOOTCFG_BASE + 0x12c)
+#define PINMUX4                        (DAVINCI_BOOTCFG_BASE + 0x130)
+#define PINMUX5                        (DAVINCI_BOOTCFG_BASE + 0x134)
+#define PINMUX6                        (DAVINCI_BOOTCFG_BASE + 0x138)
+#define PINMUX7                        (DAVINCI_BOOTCFG_BASE + 0x13c)
+#define PINMUX8                        (DAVINCI_BOOTCFG_BASE + 0x140)
+#define PINMUX9                        (DAVINCI_BOOTCFG_BASE + 0x144)
+#define PINMUX10               (DAVINCI_BOOTCFG_BASE + 0x148)
+#define PINMUX11               (DAVINCI_BOOTCFG_BASE + 0x14c)
+#define PINMUX12               (DAVINCI_BOOTCFG_BASE + 0x150)
+#define PINMUX13               (DAVINCI_BOOTCFG_BASE + 0x154)
+#define PINMUX14               (DAVINCI_BOOTCFG_BASE + 0x158)
+#define PINMUX15               (DAVINCI_BOOTCFG_BASE + 0x15C)
+#define PINMUX16               (DAVINCI_BOOTCFG_BASE + 0x160)
+#define PINMUX17               (DAVINCI_BOOTCFG_BASE + 0x164)
+#define PINMUX18               (DAVINCI_BOOTCFG_BASE + 0x168)
+#define PINMUX19               (DAVINCI_BOOTCFG_BASE + 0x16c)
+#define SUSPSRC                        (DAVINCI_BOOTCFG_BASE + 0x170)
+#define CFGCHIP0               (DAVINCI_BOOTCFG_BASE + 0x17c)
+#define CFGCHIP2               (DAVINCI_BOOTCFG_BASE + 0x184)
+
+/* Interrupt controller */
+#define INTC_GLB_EN            (DAVINCI_INTC_BASE + 0x10)
+#define INTC_HINT_EN           (DAVINCI_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0           (DAVINCI_INTC_BASE + 0x380)
+
+/* GPIO */
+#define GPIO_BANK4_ADDR                        0x01E26000
+#define GPIO_BANK4_REG_DIR_ADDR                (GPIO_BANK4_ADDR + 0x60)
+#define GPIO_BANK4_REG_OPDATA_ADDR     (GPIO_BANK4_ADDR + 0x64)
+#define GPIO_BANK4_REG_SET_ADDR                (GPIO_BANK4_ADDR + 0x68)
+#define GPIO_BANK4_REG_CLR_ADDR                (GPIO_BANK4_ADDR + 0x6C)
+
+/* Emulation suspend bits */
+#define SUSPSRC_EMAC           (1 << 5)
+#define SUSPSRC_I2C            (1 << 16)
+#define SUSPSRC_SPI0           (1 << 21)
+#define SUSPSRC_UART2          (1 << 20)
+#define SUSPSRC_TIMER0         (1 << 27)
+
+/* UART PWREMU_MGMT definitions */
+#define PWREMU_MGMT_BASE       (0x30)
+#define PWREMU_MGMT_FREE       (1 << 0)
+#define PWREMU_MGMT_URRST      (1 << 13)
+#define PWREMU_MGMT_UTRST      (1 << 14)
+
+#endif /* CONFIG_SOC_DA8XX */
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/i2c_defs.h 
b/include/asm-arm/arch-davinci/i2c_defs.h
index 2e902e1..0655d89 100644
--- a/include/asm-arm/arch-davinci/i2c_defs.h
+++ b/include/asm-arm/arch-davinci/i2c_defs.h
@@ -28,7 +28,11 @@
 #define I2C_WRITE              0
 #define I2C_READ               1
 
+#ifndef CONFIG_SOC_DA8XX
 #define I2C_BASE               0x01c21000
+#else
+#define I2C_BASE               0x01c22000
+#endif
 
 #define        I2C_OA                  (I2C_BASE + 0x00)
 #define I2C_IE                 (I2C_BASE + 0x04)
@@ -88,6 +92,9 @@
 #define I2C_CON_XA     (1 << 8)        /* Expand address */
 #define I2C_CON_STP    (1 << 11)       /* Stop condition (master mode only) */
 #define I2C_CON_STT    (1 << 13)       /* Start condition (master mode only) */
+#ifdef CONFIG_SOC_DA8XX
+#define I2C_CON_FREE   (1 << 14)       /* Free run on emulation */
+#endif
 
 #define I2C_TIMEOUT    0xffff0000      /* Timeout mask for poll_i2c_irq() */
 
diff --git a/include/common.h b/include/common.h
index f7c93bf..39765e6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -107,6 +107,9 @@ typedef volatile unsigned char      vu_char;
 #ifdef CONFIG_BLACKFIN
 #include <asm/blackfin.h>
 #endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
 
 #include <part.h>
 #include <flash.h>
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
new file mode 100644
index 0000000..2a2cd20
--- /dev/null
+++ b/include/configs/da830evm.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <k...@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS               /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ          24000000
+#define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK            clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ                  1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT     /* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN  (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE       128 /* reserved for initial data */
+#define PHYS_SDRAM_1           DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE      0x04000000 /* SDRAM size 64MB */
+#define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1 /* memtest start addr */
+#define CONFIG_SYS_MEMTEST_END         (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB 
test */
+#define CONFIG_NR_DRAM_BANKS   1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE       (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    -4      /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1        DAVINCI_UART2_BASE /* Base address of 
UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX      1               /* use UART0 for console */
+#define CONFIG_BAUDRATE                115200          /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED           25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_I2C_SLAVE           10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND          /* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET              0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE                        (128 << 10)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_CS             3
+#define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK            0x10
+#define CONFIG_SYS_ALE_MASK            0x8
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS                 1
+#define DEF_BOOTM                      ""
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS     1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ       (64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET              (CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE          DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE                        (32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE           CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        (16 << 10)
+#define CONFIG_ENV_OFFSET              (256 << 10)
+#define CONFIG_ENV_SECT_SIZE           4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE            DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK             clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED                50000000
+#define CONFIG_SYS_ENV_SPI_MAX_HZ      CONFIG_SF_DEFAULT_SPEED
+#endif
+
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_USE_IRQ                  /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE                "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT      "DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE   /* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR  (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS                "mem=32M console=ttyS2,115200n8 
root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND     ""
+#define CONFIG_BOOTDELAY       3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+       !defined(CONFIG_USE_NOR) && \
+       !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE                (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+#define CONFIG_CMD_USB         /* include support for usb      */
+#define CONFIG_CMD_STORAGE     /* include support for usb      */
+#define CONFIG_CMD_FAT         /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION   /* include support for FAT/storage*/
+#endif
+
+#endif /* __CONFIG_H */
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