On Thu, Mar 30, 2017 at 8:08 AM, Ley Foon Tan <ley.foon....@intel.com> wrote:
> Restructure misc driver in the preparation to support A10.
> Move the Gen5 specific code to gen5 file. No functional change.
>
> Change all uint32_t_to u32.
>
> Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
> ---
> arch/arm/mach-socfpga/Makefile | 2 +-
> arch/arm/mach-socfpga/include/mach/misc.h | 25 ++
> arch/arm/mach-socfpga/misc.c | 361
> ++------------------------
> arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 149 ++---------
> 4 files changed, 60 insertions(+), 477 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
> copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (73%)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 4980e51..e83da2e 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -15,7 +15,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> # QTS-generated config file wrappers
> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
> clock_manager_gen5.o
> reset_manager_gen5.o \
> - system_manager_gen5.o
> + misc_gen5.o system_manager_gen5.o
> obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
> wrap_sdram_config.o
> CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> b/arch/arm/mach-socfpga/include/mach/misc.h
> new file mode 100644
> index 0000000..f344749
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -0,0 +1,25 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
In the reset_manager_gen5.h file, patch #02, you are still using
Altera in the header and it was GPL-2.0+ license.
Now you're using Intel and GPL-2.0, I'm not sure which is right, but I
think it should be Intel for all new files?
Let's be consistent?
Dinh
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