From: Jagan Teki <ja...@amarulasolutions.com>

Add initial devicetree support for i.MX6 Quad Sabresd board.

Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@nxp.com>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 board/freescale/mx6sabresd/MAINTAINERS  |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 122 +++++++++++++++++++++-----------
 configs/imx6q_sabresd_defconfig         |  59 +++++++++++++++
 include/configs/mx6sabresd.h            |   4 ++
 4 files changed, 146 insertions(+), 40 deletions(-)
 create mode 100644 configs/imx6q_sabresd_defconfig

diff --git a/board/freescale/mx6sabresd/MAINTAINERS 
b/board/freescale/mx6sabresd/MAINTAINERS
index add2314..434548a 100644
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -6,3 +6,4 @@ F:      include/configs/mx6sabresd.h
 F:     configs/mx6dlsabresd_defconfig
 F:     configs/mx6qsabresd_defconfig
 F:     configs/mx6sabresd_spl_defconfig
+F:     configs/imx6q_sabresd_defconfig
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 80a7789..db25dad 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -241,7 +241,7 @@ static void setup_iomux_uart(void)
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_OF_CONTROL)
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
        {USDHC2_BASE_ADDR},
        {USDHC3_BASE_ADDR},
@@ -276,9 +276,9 @@ int board_mmc_getcd(struct mmc *mmc)
        return ret;
 }
 
+#ifndef CONFIG_FSL_ESDHC
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
        int ret;
        int i;
 
@@ -321,46 +321,9 @@ int board_mmc_init(bd_t *bis)
        }
 
        return 0;
-#else
-       struct src *psrc = (struct src *)SRC_BASE_ADDR;
-       unsigned reg = readl(&psrc->sbmr1) >> 11;
-       /*
-        * Upon reading BOOT_CFG register the following map is done:
-        * Bit 11 and 12 of BOOT_CFG register can determine the current
-        * mmc port
-        * 0x1                  SD1
-        * 0x2                  SD2
-        * 0x3                  SD4
-        */
-
-       switch (reg & 0x3) {
-       case 0x1:
-               imx_iomux_v3_setup_multiple_pads(
-                       usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-               usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-               break;
-       case 0x2:
-               imx_iomux_v3_setup_multiple_pads(
-                       usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-               usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-               break;
-       case 0x3:
-               imx_iomux_v3_setup_multiple_pads(
-                       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-               usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
-               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-               break;
-       }
-
-       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
 }
 #endif
+#endif
 
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
@@ -717,6 +680,85 @@ int checkboard(void)
 #include <spl.h>
 #include <libfdt.h>
 
+#ifdef CONFIG_FSL_ESDHC
+
+#if defined(CONFIG_OF_CONTROL) && !defined(CONFIG_DM_MMC)
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR},
+       {USDHC3_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_get_env_dev(int devno)
+{
+       return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = !gpio_get_value(USDHC3_CD_GPIO);
+               break;
+       case USDHC4_BASE_ADDR:
+               ret = 1; /* eMMC/uSDHC4 is always present */
+               break;
+       }
+
+       return ret;
+}
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+       struct src *psrc = (struct src *)SRC_BASE_ADDR;
+       unsigned reg = readl(&psrc->sbmr1) >> 11;
+       /*
+        * Upon reading BOOT_CFG register the following map is done:
+        * Bit 11 and 12 of BOOT_CFG register can determine the current
+        * mmc port
+        * 0x1                  SD1
+        * 0x2                  SD2
+        * 0x3                  SD4
+        */
+
+       switch (reg & 0x3) {
+       case 0x1:
+               imx_iomux_v3_setup_multiple_pads(
+                       usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+               usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+               break;
+       case 0x2:
+               imx_iomux_v3_setup_multiple_pads(
+                       usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+               usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+               break;
+       case 0x3:
+               imx_iomux_v3_setup_multiple_pads(
+                       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+               usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+               break;
+       }
+
+       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
diff --git a/configs/imx6q_sabresd_defconfig b/configs/imx6q_sabresd_defconfig
new file mode 100644
index 0000000..3919231
--- /dev/null
+++ b/configs/imx6q_sabresd_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 598ab9a..9885a5c 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -11,6 +11,10 @@
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+#  undef CONFIG_DM_GPIO
+#  undef CONFIG_DM_MMC
+# endif
 #endif
 
 #define CONFIG_MACH_TYPE       3980
-- 
1.9.1

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