On Tue, Mar 21, 2017 at 7:13 AM, Rick Altherr <ralth...@google.com> wrote:
> +Joel
>
> On Mon, Mar 20, 2017 at 10:52 AM, Maxim Sloyko <max...@google.com> wrote:
>> On Mon, Mar 20, 2017 at 10:30 AM, Tom Rini <tr...@konsulko.com> wrote:
>>> So this applies to a lot of parts of the series here. What we don't
>>> want to do is have places where the DTS here diverges from the Linux
>>> kernel DTS and we don't reconcile them. If the relevant Linux drivers
>>> are not in mainline, are they at least in linux-next or otherwise
>>> submitted to the relevant subtrees?
>>
>>
>> No, as far as I know, maybe Rick (cc'ed) knows what is the plan there.
>>
>> I'm not really working on the linux driver and it's outside of my control.
>>
>
> Looks like the Aspeed SDK version of U-Boot was configuring D2PLL as
> part of platform_g5.S
> (https://github.com/openbmc/u-boot/blob/v2016.07-aspeed-openbmc/arch/arm/mach-aspeed/platform_g5.S).
> OpenBMC kernel doesn't seem to have any clock drivers for these PLLs.
> I assume that since they were enabled by U-Boot, the ftgmac100 driver
> doesn't need to do anything for it to work. It should be
> straightforward to follow the pattern of the other clock drivers in
> https://github.com/openbmc/linux/blob/dev-4.7/arch/arm/boot/dts/aspeed-g5.dtsi
> and create a new driver for D2PLL.
We don't have clock drivers upstream. I submitted them about a year
ago, they got naked, and I haven't got around to resubmititng them.
I have reworked them in our upcoming 4.10 tree. The device tree
currently looks like this. Note that I haven't sent this version of
the patches out for review, so it may change again.
syscon: syscon@1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
clk_clkin: clk_clkin@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-clkin-clock";
reg = <0x70>;
};
clk_hpll: clk_hpll@24 {
#clock-cells = <0>;
compatible = "aspeed,g5-hpll-clock";
reg = <0x24>;
clocks = <&clk_clkin>;
};
clk_ahb: clk_ahb@70 {
#clock-cells = <0>;
compatible = "aspeed,g5-ahb-clock";
reg = <0x70>;
clocks = <&clk_hpll>;
};
clk_apb: clk_apb@08 {
#clock-cells = <0>;
compatible = "aspeed,g5-apb-clock";
reg = <0x08>;
clocks = <&clk_hpll>;
};
We don't (yet) have anything in there for the D2PLL as Linux hasn't
needed to touch them.
I recently requested detailed clock documentation from Aspeed. I will
use this to add bindings for all of the clocks in the Aspeed SoC.
Cheers,
Joel
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