On Monday 19 October 2009 16:16:02 Stefan Roese wrote: > PPC440EP(x)/PPC440GR(x): > In asynchronous PCI mode, the synchronous PCI clock must meet > certain requirements. The following equation describes the > relationship that must be maintained between the asynchronous PCI > clock and synchronous PCI clock. Select an appropriate PCI:PLB > ratio to maintain the relationship: > > AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz > > This patch now adds a function to check and reconfigure the sync > PCI clock to meet this requirement. This is in preparation for > some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this > function to not violate the PCI clocking rules.
Patch series (1...4) applied to u-boot-ppc4xx/master. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
