On Mon, Jan 30, 2017 at 11:35:04AM -0800, max...@google.com wrote: > Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. > Without this fix, valid setting can lead to division by zero > when requesting the rate of H-PLL or M-PLL clocks. > > Signed-off-by: Maxim Sloyko <max...@google.com> > Reviewed-by: Simon Glass <s...@chromium.org>
Applied to u-boot/master, thanks! -- Tom
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