On Mon, Jan 30, 2017 at 11:35:04AM -0800, [email protected] wrote: > Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. > Without this fix, valid setting can lead to division by zero > when requesting the rate of H-PLL or M-PLL clocks. > > Signed-off-by: Maxim Sloyko <[email protected]> > Reviewed-by: Simon Glass <[email protected]>
Applied to u-boot/master, thanks! -- Tom
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
