Hello guys,

This is a derivative of my previous post for adapting mpc8xxx_spi to work with 
mpc8360e spi in cpu-mode.

I'm seeing something funny with using the 'sf probe' command, but not the sspi 
command.

Using 'sspi' command, I got a good response:

=> sspi 0 32 9f
spi_xfer: tx 9f000000 [32 of 32] bits
spi_xfer: ... 9f000000 written
[0] iR 0 ev 3 <-- [tm] isRead spi->event
[0] spi_xfer: rx 1fffa270 = ff202013
spi_xfer: transfer ended. Value=ff202013
*** spi_xfer: exit
FF202013
=>


When using 'sf probe', only the first tx data got transmitted (verified with 
scope):

sf probe 0:0
spi_xfer: tx 9fffd600 [8 of 8] bits
spi_xfer: ... 9fffd600 written
[0] iR 0 ev 3 <-- [tm] isRead spi->event
[0] spi_xfer: rx 00000000 = ffff0001
spi_xfer: transfer ended. Value=ffff0001
*** spi_xfer: exit
spi_xfer: tx 000102ff [32 of 40] bits
spi_xfer: ... 000102ff written <-- Never got sent out!
[0] iR 0 ev 1 <-- [tm] isRead spi->event
[1] iR 0 ev 1 <-- [tm] isRead spi->event
[2] iR 0 ev 1 <-- [tm] isRead spi->event
...
[1000] iR 0 ev 1
*** spi_xfer: Time out during SPI transfer
spi_xfer: transfer ended. Value=00000000
spi_xfer: tx 03ffffff [8 of 8] bits
spi_xfer: ... 03ffffff written <-- Never got sent out!
[0] spi_xfer: rx 1f5b4da8 = 13000000
spi_xfer: transfer ended. Value=13000000
*** spi_xfer: exit
SF: Got idcode 13 00 00 00 00
Failed to initialize SPI flash at 0:0
=>

On the oscilloscope, even though "spi_xfer: ... 000102ff written" is shown,
I only see the first byte (9f) being sent and the clock stops there, explaining 
the debug printout during getting
rx data that shows the rx buffer never got any data

I have tried replacing the spi->tx = tmpdout statement (and all register access) with 
out_be##(&spi->tx, tmpdout)
in case the compiler is optimizing things out, but this makes no difference.

but if this is true, won't the MPC8349EMDS see this problem also?

What am I missing here?

Modified driver is attached.

Thanks for all the help!

- Richard


/*
 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
 * With help from the common/soft_spi and cpu/mpc8260 drivers
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#include <malloc.h>
#include <spi.h>
#include <asm/mpc8xxx_spi.h>

#if defined (CONFIG_MPC8360)
#include <asm/immap_qe.h>
#endif

#if defined (CONFIG_MPC8360)
#define SPI_EV_LT	(0x80 >> 1)	/* Last char transmitted */
#define SPI_EV_NE	(0x80 >> 6)	/* Receiver Not Empty */
#define SPI_EV_NF	(0x80 >> 7)	/* Transmitter Not Full */

#define SPI_COM_LST	(0x80 >> 1)	/* Last char in frame */

#else
#define SPI_EV_LT	(0x80000000 >> 17)	/* Last char transmitted */
#define SPI_EV_NE	(0x80000000 >> 22)	/* Receiver Not Empty */
#define SPI_EV_NF	(0x80000000 >> 23)	/* Transmitter Not Full */

#define SPI_COM_LST	(0x80000000 >> 9)	/* Last char in frame */
#endif

#define SPI_MODE_LOOP	(0x80000000 >> 1)	/* Loopback mode */
#define SPI_MODE_CI	(0x80000000 >> 2)	/* Clock Invert */
#define SPI_MODE_CP	(0x80000000 >> 3)	/* Clock Phase */
#define SPI_MODE_DIV16	(0x80000000 >> 4)	/* Input clock divider */
#define SPI_MODE_REV	(0x80000000 >> 5)	/* Reverse mode - MSB first */
#define SPI_MODE_MS	(0x80000000 >> 6)	/* Always master */
#define SPI_MODE_EN	(0x80000000 >> 7)	/* Enable interface */
#define SPI_MODE_OP	(0x80000000 >> 17)	/* CPU mode (MPC8360E only) */

#define SPI_TIMEOUT	1000000

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	struct spi_slave *slave;
#if defined (CONFIG_MPC8360)
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe;
	volatile spi_t *spi = (volatile spi_t *)&qe->spi[0];
#endif

	if (!spi_cs_is_valid(bus, cs))
		return NULL;

	slave = malloc(sizeof(struct spi_slave));
	if (!slave)
		return NULL;

	slave->bus = bus;
	slave->cs = cs;

	/*
	 * TODO: Some of the code in spi_init() should probably move
	 * here, or into spi_claim_bus() below.
	 */

#if defined (CONFIG_MPC8360)
	/* Mode must be CPU mode to use this driver */
	spi->mode = SPI_MODE_DIV16 | SPI_MODE_REV | SPI_MODE_MS |
			SPI_MODE_EN | SPI_MODE_OP;

	/* Set speed to (QE_CLK/640) = 625 KHz */
	spi->mode = (spi->mode & 0xfff0ffff) | (4 << 16);
	spi->event = 0xff; /* Clear all SPI events */
	spi->mask = 0x00; /* Mask  all SPI interrupts */
	spi->com = 0; /* LST bit doesn't do anything, so disregard */
#endif
	return slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	free(slave);
}

void spi_init(void)
{
	/*
	 * Doing SPI controller setup in spi_init for mpc8360e has no effect,
	 * the settings got reset back to defaults by some other initialization
	 * call later (qe_reset?) do it spi_setup_slave.
	 */
#if !defined (CONFIG_MPC8360)
	volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;

	/*
	 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
	 * some registers
	 */
	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
	spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
							     (16.67MHz typ.) */
	spi->event = 0xffffffff;	/* Clear all SPI events */
	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */
	spi->com = 0;		/* LST bit doesn't do anything, so disregard */
#endif
}

int spi_claim_bus(struct spi_slave *slave)
{
#if defined (CONFIG_MPC8360)
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe;
	volatile spi_t *spi = (volatile spi_t *)&qe->spi[0];
#else
	volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
#endif
	/* Enable the SPI controller */
	spi->mode |= SPI_MODE_EN;

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
#if defined (CONFIG_MPC8360)
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe;
	volatile spi_t *spi = (volatile spi_t *)&qe->spi[0];
#else
	volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
#endif
	/* Disable the SPI controller */
	spi->mode &= ~(SPI_MODE_EN);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	u32 tmpdout = 0;
	u32 tmpdin = 0;
	u32 numBlks = (bitlen / 32) + (bitlen % 32 ? 1 : 0);
	u32 tm, isRead = 0;
	u8 charSize = 32;

#if defined (CONFIG_MPC8360)
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile qe_map_t *qe = (volatile qe_map_t *)&im->qe;
	volatile spi_t *spi = (volatile spi_t *)&qe->spi[0];
	u8 event;
#else
	volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
	u32 event;
#endif

#if defined (CONFIG_MPC8360)
	spi->event = 0xff;	/* Clear all SPI events */
#else
	spi->event = 0xffffffff; /* Clear all SPI events */
#endif

	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
	      slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	/* handle data in 32-bit chunks */
	while (numBlks--) {
		tmpdout = 0;
		charSize = (bitlen >= 32 ? 32 : bitlen);

		/* tx data must always be 32-bit aligned */
#if defined (CONFIG_MPC8360)
		tmpdout = *(u32 *) dout;
#else
		/* Shift data so it's msb-justified */
		tmpdout = *(u32 *) dout >> (32 - charSize);
#endif

		printf("spi_xfer: tx %08x [%d of %d] bits\n",
		       tmpdout, charSize, bitlen);

		/* The LEN field of the SPMODE register is set as follows:
		 *
		 * Bit length             setting
		 * len <= 4               3
		 * 4 < len <= 16          len - 1
		 * len > 16               0
		 */
		if (bitlen <= 16) {
			if (bitlen <= 4)
				spi->mode = (spi->mode & 0xff0fffff) |
				            (3 << 20);
			else
				spi->mode = (spi->mode & 0xff0fffff) |
				            ((bitlen - 1) << 20);
		} else {
			spi->mode = (spi->mode & 0xff0fffff);
			/* Set up the next iteration if sending > 32 bits */
			bitlen -= 32;
			dout += 4;
		}

		/* On loops following the initial cmd, this is not written */
		spi->tx = tmpdout;
		printf("spi_xfer: ... %08x written\n", tmpdout);

		/* HACK: Delay until tx is sent 1 bit = 1.6us @ 625KHz
		 * yes, there are better ways, none seems to work now
		 */
		udelay(52); /* 1.6/bit 12.8/u8 51.2/u32 */
		/*
		 * Wait for SPI transmit to get out
		 * or time out (1 second = 1000 ms)
		 * The NE event must be read and cleared first
		 */
		for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
			event = spi->event;

			/* verbose debug print */
			printf("[%d] iR %d ev %d\n", tm, isRead, event);

			if (event & SPI_EV_NE) {
				tmpdin = spi->rx;
				spi->event |= SPI_EV_NE;
				isRead = 1;
				printf("[%d] spi_xfer: rx %08x = %08x\n",
				        tm, (u32)din, tmpdin);

				if (din != NULL) {
				#if defined (CONFIG_MPC8360)
					*(u32 *) din = tmpdin;
				#else
					*(u32 *) din = (tmpdin << (32 - charSize));
				#endif
					if (charSize == 32) {
						/* Advance output buffer by 32 bits */
						din += 4;
					}
				}
			}
			/*
			 * Only bail when we've had both NE and NF events.
			 * This will cause timeouts on RO devices, so maybe
			 * in the future put an arbitrary delay after writing
			 * the device.  Arbitrary delays suck, though...
			 */
			if (isRead && (event & SPI_EV_NF)) {
				break;
			}
		}
		if (tm >= SPI_TIMEOUT) {
			puts("*** spi_xfer: Time out during SPI transfer\n");
		}
		printf("spi_xfer: transfer ended. Value=%08x\n", tmpdin);
	}

	if (flags & SPI_XFER_END) {
		spi_cs_deactivate(slave);
	}

	puts("*** spi_xfer: exit\n");

	return 0;
}
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