On Mon, Oct 12, 2009 at 4:24 AM, Jens Gehrlein <se...@tqs.de> wrote: > Hi Alemao, > > Alemao schrieb: >> >> Hi all, >> >> I have used UPM in a MPC83xx with LBC running at 64MHz. >> >> Now I have a MPC85xx, with LBC at 41MHz. >> >> It only works if I put a delay in drivers/mtd/nand/fsl_upm.c : >> nand_write_buf(), otherwise I lost one byte. But it takes toooo long >> writing, which makes their use impractical. >> >> I saw in board/tqc/tqm85xx/nand.c that the driver use an UPM >> configuration for each frequency. >> >> Can some one tell me what signals I have to change or just some hint >> about what could be causing this behavior? >> >> Im using UPM waveform editor and u-boot-2009-03. > > The UPM tables and ORx settings for TQM85xx are optimized for each > LBC frequency, the used NAND chips and the used PCB. > > To get the right timing for *your* HW you probably need a timing > simulation before. Eventually, you have to connect a timing analyzer > and check the bus signals after. > > If the timing is correct, check the right order of bus commands, > too. The issue with the e500 core is, that it may reorder machine > instructions. Perhaps you need to instert "mbar" instructions. >
I tried to use the same frequency that I was using in my MPC83xx board, I got the same problem. Can PCB layout significantly influence at 66Mhz? Or 41MHz? Cause I had programmed UPM with the same array in both processors. What do you mean by "instert mbar instructions"? Where? > Sorry, I'm not a HW guy, so I can't tell you more. I didn't do the > simulation and analysis myself. > > Kind regards, > Jens > Thanks, -- Alemao _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
