---
Changes in v2: None
Changes in v1:
- Merge together all patches related to ast2500 boards common
functions/configs
- Add copyright statement to ast2500-board.c
Signed-off-by: Maxim Sloyko <max...@google.com>
---
arch/arm/mach-aspeed/Makefile | 2 +-
arch/arm/mach-aspeed/ast2500-board.c | 78 +++++++++++++++++++++++++++++++++
include/configs/aspeed-common.h | 84 ++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-aspeed/ast2500-board.c
create mode 100644 include/configs/aspeed-common.h
diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile
index 1f7af71b03..9d29ff7f6f 100644
--- a/arch/arm/mach-aspeed/Makefile
+++ b/arch/arm/mach-aspeed/Makefile
@@ -5,4 +5,4 @@
#
obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
-obj-$(CONFIG_ASPEED_AST2500) += ast2500/
+obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o
diff --git a/arch/arm/mach-aspeed/ast2500-board.c
b/arch/arm/mach-aspeed/ast2500-board.c
new file mode 100644
index 0000000000..6ff74f0a1f
--- /dev/null
+++ b/arch/arm/mach-aspeed/ast2500-board.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <ram.h>
+#include <timer.h>
+
+/* Second Watchdog Timer by default is configured
+ * to trigger secondary boot source.
+ */
+#define AST_2ND_BOOT_WDT (1)
+
+/* Third Watchdog Timer by default is configured
+ * to toggle Flash address mode switch before reset.
+ */
+#define AST_FLASH_ADDR_DETECT_WDT (2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void lowlevel_init(void)
+{
+ /*
+ * These two watchdogs need to be stopped as soon as possible,
+ * otherwise the board might hang. By default they are set to
+ * a very short timeout and even simple debug write to serial
+ * console early in the init process might cause them to fire.
+ */
+ struct ast_wdt *flash_addr_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_FLASH_ADDR_DETECT_WDT);
+
+ clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
+
+#ifndef CONFIG_FIRMWARE_2ND_BOOT
+ struct ast_wdt *sec_boot_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_2ND_BOOT_WDT);
+
+ clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
+#endif
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ int ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM FAIL1\r\n");
+ return ret;
+ }
+
+ struct ram_info ram;
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("DRAM FAIL2\r\n");
+ return ret;
+ }
+
+
+ gd->ram_size = ram.size;
+ return 0;
+}
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
new file mode 100644
index 0000000000..c125e39e3f
--- /dev/null
+++ b/include/configs/aspeed-common.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Ryan Chen <ryan_c...@aspeedtech.com>
+ *
+ * Copyright 2016 IBM Corporation
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AST_COMMON_CONFIG_H
+#define __AST_COMMON_CONFIG_H
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/* Enable cache controller */
+#define CONFIG_SYS_DCACHE_OFF 1
+
+#ifdef CONFIG_PRE_CON_BUF_SZ
+#define PRE_CON_RAM_SZ CONFIG_PRE_CON_BUF_SZ
+#else
+#define PRE_CON_RAM_SZ 0
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + PRE_CON_RAM_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - PRE_CON_RAM_SZ)
+#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
+ + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_BOOTARGS \
+ "console=ttyS4,115200n8" \
+ " root=/dev/ram rw"
+
+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=yes\0" \
+ "spi_dma=yes\0" \
+ ""
+
+#endif /* __AST_COMMON_CONFIG_H */
--
2.11.0.390.gc69c2f50cf-goog
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