> -----Original Message-----
> From: Zhiqiang Hou [mailto:zhiqiang....@nxp.com]
> Sent: 2016年12月27日 15:36
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> <york....@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Prabhakar
> Kushwaha <prabhakar.kushw...@nxp.com>; Calvin Johnson
> <calvin.john...@nxp.com>
> Cc: Z.Q. Hou <zhiqiang....@nxp.com>
> Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
>
> From: Hou Zhiqiang <zhiqiang....@nxp.com>
>
> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A,
> LS1046A and LS1012A. But the clocks tree has a lot of differences, for
> instance,
> the IP modules have different dividers to derive its clock from Platform PLL.
> And the core cluster PLL and platform PLL maybe have different reference
> clocks, such as LS1012A. Another problem is which clock/PLL should be
> described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
>
> This patch is to bind the sys_info->freq_systembus to the Platform PLL, and
> handle the different divider of IP modules separately between different SoCs,
> and separate reference clocks of core cluster PLL and platform PLL.
>
> Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
> ---
> V3:
> - Generate the patch set base on the latest
> git://git.denx.de/u-boot-fsl-qoriq.git.
> - Use the Kconfig instead of header file to add CONFIG_*
>
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 76
> ++++++++++++++++++++++
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +-
> .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> ++++++++++++++----- .../include/asm/arch-fsl-layerscape/immap_lsch2.h |
> 1 +
> include/configs/ls1012a_common.h | 6 +-
> include/configs/ls1043a_common.h | 3 +-
> include/configs/ls1046a_common.h | 3 +-
> include/configs/ls2080aqds.h | 2 -
> include/configs/ls2080ardb.h | 1 -
> 9 files changed, 134 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index cc0dc88..de1e5a4 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -87,6 +87,82 @@ config MAX_CPUS
> cores, count the reserved ports. This will allocate enough memory
> in spin table to properly handle all cores.
>
> +menu "Layerscape clock tree configuration"
> + depends on FSL_LSCH2 || FSL_LSCH3
> +
> +config SYS_FSL_CLK
> + bool "Enable clock tree initialization"
> + default y
> +
> +config CLUSTER_CLK_FREQ
> + int "Reference clock of core cluster"
> + depends on ARCH_LS1012A
> + default 100000000
> + help
> + This number is the reference clock frequency of core PLL.
> + For most platforms, the core PLL and Platform PLL have the same
> + reference clock, but for some platforms, LS1012A for instance,
> + they are provided sepatately.
> +
> +config SYS_FSL_PCLK_DIV
> + int "Platform clock divider"
> + default 1 if ARCH_LS1043A
> + default 1 if ARCH_LS1046A
> + default 2
> + help
> + This is the divider that is used to derive Platform clock from
> + Platform PLL, in another word:
> + Platform_clk = Platform_PLL_freq / this_divider
> +
> +config SYS_FSL_DSPI_CLK_DIV
> + int "DSPI clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive DSPI clock from Platform
> + PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
There is a description error, the IP modules' clock should be derived from
Platform clock instead of Platform PLL. Will fix next version.
> +
> +config SYS_FSL_DUART_CLK_DIV
> + int "DUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive DUART clock from Platform
> + PLL, in another word DUART_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_I2C_CLK_DIV
> + int "I2C clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive I2C clock from Platform
> + PLL, in another word I2C_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_IFC_CLK_DIV
> + int "IFC clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive IFC clock from Platform
> + PLL, in another word IFC_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_LPUART_CLK_DIV
> + int "LPUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive LPUART clock from Platform
> + PLL, in another word LPUART_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_SDHC_CLK_DIV
> + int "SDHC clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> + This is the divider that is used to derive SDHC clock from Platform
> + PLL, in another word SDHC_clk = Platform_PLL_freq / this_divider.
> +endmenu
> +
> config NUM_DDR_CONTROLLERS
> int "Maximum DDR controllers"
> default 3 if ARCH_LS2080A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 467d9af..3bdeb0e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -345,8 +345,9 @@ int print_cpuinfo(void)
> (type == TY_ITYP_VER_A72 ? "A72" : " "))),
> strmhz(buf, sysinfo.freq_processor[core]));
> }
> + /* Display platform clock as Bus frequency. */
> printf("\n Bus: %-4s MHz ",
> - strmhz(buf, sysinfo.freq_systembus));
> + strmhz(buf, sysinfo.freq_systembus /
> CONFIG_SYS_FSL_PCLK_DIV));
> printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
> #ifdef CONFIG_SYS_DPAA_FMAN
> printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> index 55005f0..f216231 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
> uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
> uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
> unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
> + unsigned long cluster_clk;
>
> sys_info->freq_systembus = sysclk;
> +#ifndef CONFIG_CLUSTER_CLK_FREQ
> +#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
> +#endif
> + cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
> +
> #ifdef CONFIG_DDR_CLK_FREQ
> sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else
> sys_info->freq_ddrbus = sysclk;
> #endif
>
> -#ifdef CONFIG_ARCH_LS1012A
> - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> -#else
> + /* The freq_systembus is used to record frequency of platform PLL */
> sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> +
> +#ifdef CONFIG_ARCH_LS1012A
> + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; #else
> sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
> for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
> ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
> if (ratio[i] > 4)
> - freq_c_pll[i] = sysclk * ratio[i];
> + freq_c_pll[i] = cluster_clk * ratio[i];
> else
> freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
> }
> @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
> freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
> }
>
> -#ifdef CONFIG_ARCH_LS1012A
> - sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
> - sys_info->freq_ddrbus *= 2;
> -#endif
> -
> #define HWA_CGA_M1_CLK_SEL 0xe0000000
> #define HWA_CGA_M1_CLK_SHIFT 29
> #ifdef CONFIG_SYS_DPAA_FMAN
> @@ -148,7 +149,8 @@ void get_sys_info(struct sys_info *sys_info)
> break;
> }
> #else
> - sys_info->freq_sdhc = sys_info->freq_systembus;
> + sys_info->freq_sdhc = sys_info->freq_systembus /
> + CONFIG_SYS_FSL_SDHC_CLK_DIV;
> #endif
> #endif
>
> @@ -166,7 +168,7 @@ int get_clocks(void)
>
> get_sys_info(&sys_info);
> gd->cpu_clk = sys_info.freq_processor[0];
> - gd->bus_clk = sys_info.freq_systembus;
> + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
> gd->mem_clk = sys_info.freq_ddrbus;
>
> #ifdef CONFIG_FSL_ESDHC
> @@ -179,41 +181,73 @@ int get_clocks(void)
> return 1;
> }
>
> +/********************************************
> + * get_bus_freq
> + * return platform clock in Hz
> + *********************************************/
> ulong get_bus_freq(ulong dummy)
> {
> + if (!gd->bus_clk)
> + get_clocks();
> +
> return gd->bus_clk;
> }
>
> ulong get_ddr_freq(ulong dummy)
> {
> + if (!gd->mem_clk)
> + get_clocks();
> +
> return gd->mem_clk;
> }
>
> #ifdef CONFIG_FSL_ESDHC
> int get_sdhc_freq(ulong dummy)
> {
> + if (!gd->arch.sdhc_clk)
> + get_clocks();
> +
> return gd->arch.sdhc_clk;
> }
> #endif
>
> int get_serial_clock(void)
> {
> - return gd->bus_clk;
> + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; }
> +
> +int get_i2c_freq(ulong dummy)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; }
> +
> +int get_dspi_freq(ulong dummy)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
> }
>
> +#ifdef CONFIG_FSL_LPUART
> +int get_uart_freq(ulong dummy)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV; } #endif
> +
> unsigned int mxc_get_clock(enum mxc_clock clk) {
> switch (clk) {
> case MXC_I2C_CLK:
> - return get_bus_freq(0);
> + return get_i2c_freq(0);
> #if defined(CONFIG_FSL_ESDHC)
> case MXC_ESDHC_CLK:
> return get_sdhc_freq(0);
> #endif
> case MXC_DSPI_CLK:
> - return get_bus_freq(0);
> + return get_dspi_freq(0);
> +#ifdef CONFIG_FSL_LPUART
> case MXC_UART_CLK:
> - return get_bus_freq(0);
> + return get_uart_freq(0);
> +#endif
> default:
> printf("Unsupported clock\n");
> }
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index b3cfd89..6ace3da 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -137,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or
> CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
>
> struct sys_info {
> unsigned long freq_processor[CONFIG_MAX_CPUS];
> + /* frequency of platform PLL */
> unsigned long freq_systembus;
> unsigned long freq_ddrbus;
> unsigned long freq_localbus;
> diff --git a/include/configs/ls1012a_common.h
> b/include/configs/ls1012a_common.h
> index 20f0c61..910835e 100644
> --- a/include/configs/ls1012a_common.h
> +++ b/include/configs/ls1012a_common.h
> @@ -19,9 +19,7 @@
>
> #define CONFIG_SYS_TEXT_BASE 0x40100000
>
> -#define CONFIG_SYS_FSL_CLK
> -#define CONFIG_SYS_CLK_FREQ 100000000
> -#define CONFIG_DDR_CLK_FREQ 125000000
> +#define CONFIG_SYS_CLK_FREQ 125000000
>
> #define CONFIG_SKIP_LOWLEVEL_INIT
> #define CONFIG_BOARD_EARLY_INIT_F 1
> @@ -82,7 +80,7 @@
> #define CONFIG_CONS_INDEX 1
> #define CONFIG_SYS_NS16550_SERIAL
> #define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
> +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
>
> #define CONFIG_BAUDRATE 115200
> #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
> 115200 }
> diff --git a/include/configs/ls1043a_common.h
> b/include/configs/ls1043a_common.h
> index c1e3ec6..f7a4397 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -11,7 +11,6 @@
> #define CONFIG_FSL_LAYERSCAPE
> #define CONFIG_LS1043A
> #define CONFIG_MP
> -#define CONFIG_SYS_FSL_CLK
> #define CONFIG_GICV2
>
> #include <asm/arch/config.h>
> @@ -42,7 +41,7 @@
> #define CONFIG_CONS_INDEX 1
> #define CONFIG_SYS_NS16550_SERIAL
> #define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
> +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
>
> #define CONFIG_BAUDRATE 115200
> #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
> 115200 }
> diff --git a/include/configs/ls1046a_common.h
> b/include/configs/ls1046a_common.h
> index 3887faa..b51e8bf 100644
> --- a/include/configs/ls1046a_common.h
> +++ b/include/configs/ls1046a_common.h
> @@ -10,7 +10,6 @@
> #define CONFIG_REMAKE_ELF
> #define CONFIG_FSL_LAYERSCAPE
> #define CONFIG_MP
> -#define CONFIG_SYS_FSL_CLK
> #define CONFIG_GICV2
>
> #include <asm/arch/config.h>
> @@ -41,7 +40,7 @@
> #define CONFIG_CONS_INDEX 1
> #define CONFIG_SYS_NS16550_SERIAL
> #define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
> +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
>
> #define CONFIG_BAUDRATE 115200
> #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
> 115200 }
> diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index
> 838568f..793e1ac 100644
> --- a/include/configs/ls2080aqds.h
> +++ b/include/configs/ls2080aqds.h
> @@ -14,8 +14,6 @@ unsigned long get_board_sys_clk(void); unsigned long
> get_board_ddr_clk(void); #endif
>
> -#define CONFIG_SYS_FSL_CLK
> -
> #ifdef CONFIG_FSL_QSPI
> #define CONFIG_SYS_NO_FLASH
> #undef CONFIG_CMD_IMLS
> diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index
> 31df781..76e8622 100644
> --- a/include/configs/ls2080ardb.h
> +++ b/include/configs/ls2080ardb.h
> @@ -32,7 +32,6 @@
> unsigned long get_board_sys_clk(void);
> #endif
>
> -#define CONFIG_SYS_FSL_CLK
> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
> #define CONFIG_DDR_CLK_FREQ 133333333
> #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
> --
> 2.1.0.27.g96db324
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